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Recent questions tagged 8085-microprocessor

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UGC NET CSE | January 2017 | Part 2 | Question: 34
The contents of Register $(BL)$ and Register $(AL)$ of $8085$ microprocessor are $49H$ and $3AH$ respectively. The contents of $AL$, the status of carry flag $(CF)$ and sign flag $(SF)$ after executing $'SUB AL, BL'$ ... $AL =F1H; \: CF = 1; \: SF= 1$ $AL =1FH; \: CF=1; \:SF=1$

go_editor asked in CO and Architecture Mar 24, 2020

3.7k views

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1 answer

2

Microprocessor
What are the status of the ZERO flag and the contents of the accumulator after the execution of the following 8085 assembly code? Assume that contents of all other registers and memory locations are unknown. MOV A, 65H MOV B, 32H CMP B a. 0, 00H b. 0, 65H c. 1, 00H d. 1, 65H

Abikkkaaa asked in Digital Logic Oct 15, 2018

2.0k views

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1 answer

3

Microprocessor
Which of the following flags is not affected by a conditional branch statement in an 8085 microprocessor? a. Auxiliary Carry flag b. Sign flag c. Carry flag d. Zero flag

Abikkkaaa asked in Digital Logic Oct 15, 2018

3.0k views

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7 answers

4

UGC NET CSE | July 2018 | Part 2 | Question: 100
In 8085 microprocessor, what is the output of following program? LDA 8000H MVI B, 30H ADD B STA 8001 H Read a number from input port and store it in memory Read a number from input device with address 8000H and store it ... location 8001H Load A with data from input device with address 8000H and display it on the output device with address 8001H

Pooja Khatri asked in CO and Architecture Jul 13, 2018

by Pooja Khatri

1.6k views

1 vote

1 answer

5

UGC NET CSE | November 2017 | Part 3 | Question: 3
In the architecture of $8085$ ... $\text{(a)-(ii) (b)-(iii) (c)-(i)}$ $\text{(a)-(i) (b)-(ii) (c)-(iv)}$

Arjun asked in CO and Architecture Nov 5, 2017

by Arjun

1.7k views

1 vote

0 answers

6

UGC NET CSE | November 2017 | Part 3 | Question: 2
In $8085$ microprocessor the address bus is of ___________ bits. $4$ $8$ $16$ $32$

Arjun asked in CO and Architecture Nov 5, 2017

by Arjun

2.2k views

3 votes

2 answers

7

UGC NET CSE | November 2017 | Part 3 | Question: 1
In $8085$ microprocessor which of the following flag(s) is (are) affected by an arithmetic operation? AC flag only CY flag Only Z flag Only AC, CY, Z flags

Arjun asked in CO and Architecture Nov 5, 2017

by Arjun

1.6k views

5 votes

1 answer

8

UGC NET CSE | November 2017 | Part 2 | Question: 32
Consider the following assembly program fragment: stc mov al, 11010110b mov cl,2 rcl al,3 rol al, 4 shr al, cl mul cl The contents of the destination register $ax$ (in hexadecimal ) and the status of Carry Flag (CF) after the execution of above instructions, are: $ax =003CH; \: CF=0$ $ax=001EH; \: CF=0$ $ax=007BH; \: CF=1$ $ax=00B7H; \: CF=1$

Arjun asked in CO and Architecture Nov 5, 2017

by Arjun

5.2k views

2 votes

2 answers

9

UGC NET CSE | November 2017 | Part 2 | Question: 31
Consider the following program fragment in assembly language: mov ax, 0h mov cx, 0A h do loop: dec ax loop doloop What is the value of $ax$ and $cx$ registers after the completion of the doloop ? $ax= FFF5 \: h$ and $cx=0 \:h$ $ax= FFF6 \: h$ and $cx=0 \: h$ $ax= FFF7 \: h$ and $cx=0A \:h$ $ax=FFF5 \: h$ and $cx=0A \: h$

Arjun asked in CO and Architecture Nov 5, 2017

by Arjun

6.1k views

9 votes

2 answers

10

ISRO2017-20
Which interrupt in $8085$ Microprocessor is unmaskable? $\textsf{RST 5.5}$ $\textsf{RST 7.5}$ $\textsf{TRAP}$ Both (a) and (b)

sh!va asked in CO and Architecture May 7, 2017

by sh!va

4.3k views

0 votes

0 answers

11

8085 uP
if the number starts with a letter of the alphabet, you need to add a zero before it. For example, AB is entered as 0abh. WHY?

Epsilon95 asked in Digital Logic May 4, 2017

701 views

1 vote

1 answer

12

ISRO2012-ECE 8085 processor
The complement Accumulator (CMA) instruction in $8085$ processor on execution affects Zero flag Sign flag Overflow flag none of the above

sh!va asked in CO and Architecture Feb 27, 2017

by sh!va

1.2k views

2 votes

1 answer

13

ISRO2012-ECE: Computer Architecture
The register in $8085$ that is used to keep track of the memory address of the next opcode to be run in the program is the: Stack Pointer Program Counter Accumulator Non of the above

sh!va asked in CO and Architecture Feb 27, 2017

by sh!va

518 views

2 votes

1 answer

14

GATE CSE 1988 | Question: 1iv
If the total number of states in the fetching and execution phases of an $8085$ instruction is known to be $7,$ number of states in these machine cycles is divided as ________

go_editor asked in Others Dec 10, 2016

779 views

1 vote

1 answer

15

UGC NET CSE | August 2016 | Part 3 | Question: 4
Which of the following in 8085 microprocessor performs $HL = HL + HL$ ? DAD D DAD H DAD B DAD SP

makhdoom ghaya asked in CO and Architecture Sep 30, 2016

by makhdoom ghaya

609 views

1 vote

0 answers

16

UGC NET CSE | August 2016 | Part 3 | Question: 2
$8085$ microprocessor has ____ bit ALU. $32$ $16$ $8$ $4$

makhdoom ghaya asked in CO and Architecture Sep 30, 2016

by makhdoom ghaya

839 views

1 vote

1 answer

17

UGC NET CSE | August 2016 | Part 2 | Question: 32
The content of the accumulator after the execution of the following 8085 assembly language program, is MVI A, 35H MOV B, A STC CMC RAR XRA B $00H$ $35H$ $EFH$ $2FH$

makhdoom ghaya asked in CO and Architecture Sep 26, 2016

by makhdoom ghaya

6.1k views

1 vote

1 answer

18

UGC NET CSE | December 2010 | Part 2 | Question: 35
Macro-processors are ______. Hardware Compiler Registers None of the above

makhdoom ghaya asked in CO and Architecture Sep 8, 2016

by makhdoom ghaya

2.6k views

3 votes

1 answer

19

UGC NET CSE | December 2015 | Part 3 | Question: 3
Which of the following $8085$ microprocessor hardware interrupt has the lowest priority? RST $6.5$ RST $7.5$ TRAP INTR

go_editor asked in Unknown Category Aug 9, 2016

5.9k views

2 votes

1 answer

20

UGC NET CSE | Junet 2015 | Part 3 | Question: 3
The RST 7 instruction in 8085 microprocessor is equal to CALL 0010 H CALL 0034 H CALL 0038 H CALL 003C H

go_editor asked in CO and Architecture Jul 31, 2016

3.7k views

1 vote

1 answer

21

UGC NET CSE | December 2014 | Part 3 | Question: 06
Specify the contents of the accumulator and the status of the $S, Z$ and $CY$ flags when $8085$ microprocessor performs addition of $87 H$ and $79 H$. $11, 1, 1, 1$ $10, 0, 1, 0$ $01, 1, 0, 0$ $00, 0, 1, 1$

makhdoom ghaya asked in CO and Architecture Jul 24, 2016

by makhdoom ghaya

6.1k views

1 vote

2 answers

22

UGC NET CSE | December 2014 | Part 3 | Question: 05
How many times will the following loop be executed ? LXI B, 0007 H LOP : DCX B MOV A, B ORA C JNZ LOP $05$ $07$ $09$ $00$

makhdoom ghaya asked in CO and Architecture Jul 24, 2016

by makhdoom ghaya

8.5k views

0 votes

1 answer

23

UGC NET CSE | December 2014 | Part 3 | Question: 04
Match the following $8085$ instructions with the flags $:$ ... $\text{a-ii, b-iii, c-i, d-iv}$ $\text{a-ii, b-iv, c-i, d-iii}$

makhdoom ghaya asked in CO and Architecture Jul 24, 2016

by makhdoom ghaya

2.5k views

1 vote

2 answers

24

UGC NET CSE | June 2016 | Part 3 | Question: 3
Which of the following in 8085 microprocessor performs HL=HL+DE ? DAD D DAD H DAD B DAD SP

Sanjay Sharma asked in CO and Architecture Jul 11, 2016

by Sanjay Sharma

3.0k views

5 votes

2 answers

25

ISRO2008-39
Consider the following Assembly language program MVIA 30 H ACI 30 H XRA A POP H After the execution of the above program, the contents of the accumulator will be $\textsf{30 H}$ $\textsf{60 H}$ $\textsf{00 H}$ contents of stack

go_editor asked in CO and Architecture Jun 12, 2016

3.9k views

4 votes

4 answers

26

ISRO2008-45
The TRAP is one of the interrupts available in $\textsf{INTEL 8085}.$ Which one of the following statements is true of TRAP ? it is level triggered it is negative edge triggered it is $\textsf{+ve}$ edge triggered it is both $\textsf{+ve}$ and $\textsf{-ve}$ edges triggered

jaiganeshcse94 asked in CO and Architecture Jun 1, 2016

by jaiganeshcse94

4.0k views

4 votes

5 answers

27

ISRO2015-61
The contents of the flag register after execution of the following program by $8085$ microprocessor will be $\textbf{Program}$ $\textsf{SUB A}$ $\textsf{MVI B,(01)}_\textsf{H}$ $\textsf{DCR B}$ $\textsf{HLT}$ $(54)_\textsf{H}$ $(00)_\textsf{H}$ $(01)_\textsf{H}$ $(45)_\textsf{H}$

kvkumar asked in CO and Architecture May 17, 2016

10.2k views

0 votes

2 answers

28

Sanjay Sharma asked in CO and Architecture May 3, 2016

by Sanjay Sharma

923 views

0 votes

1 answer

29

Sanjay Sharma asked in CO and Architecture May 3, 2016

by Sanjay Sharma

410 views

3 votes

2 answers

30

ISRO-2013-36
In 8085 microprocessor, the ISR for handling trap interrupt is at which location? $3CH$ $34H$ $74H$ $24H$

makhdoom ghaya asked in CO and Architecture Apr 27, 2016

by makhdoom ghaya

3.6k views

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Recent questions tagged 8085-microprocessor