Dark Mode

Recent questions tagged branch-conditional-instructions

11 votes

1 answer

1

GO Classes Test Series 2024 | Mock GATE | Test 14 | Question: 63
Assume an instruction mix of $15 \%$ conditional branches, $1 \%$ unconditional branches, $84 \%$ all others, and $60 \%$ of the conditional branches are taken. We have a 4-stage pipeline where branch target locations ... $1.38$ For both "predict taken", "predict not taken" branch predictions, CPI is the $1.30$

GO Classes asked in CO and Architecture Feb 5

740 views

2 votes

1 answer

2

GO Classes Test Series 2024 | Mock GATE | Test 13 | Question: 34
In typical RISC ISA, delayed branch executes which instruction irrespective of whether the branch condition is true or false? Instruction immediately following the branch condition Instruction immediately preceding the branch condition Instruction that belongs to a different a subroutine It waits till the branch condition is evaluated

GO Classes asked in CO and Architecture Jan 28

378 views

7 votes

3 answers

3

GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 48
Consider a processor with a branch-if-equal instruction that is $32$ bits long$\textsf{: BEQ R12, R11, X.}$ $6$ bits are used to encode the opcode, $6$ bits are used to encode one register number, $6$ bits ... $4$ bytes long. How many instructions away (the number of instructions) from the $\textsf{BEQ}$ instruction could we reach?

GO Classes asked in CO and Architecture Jan 21

620 views

0 votes

1 answer

4

COA | Branch Delays
Consider the following sequence of instructions for a pipelined processor with one branch delay slot: I1 LABEL: ADD R3 ← R3 + 1 I2 DIV R2 ← R2/R6 I3 SUB R1 ← R2-1 I4 If R1≤0 then BRANCH to LABEL I5 SUB R3 ← R3-R7 Which of the following is true after ... now label pointing to I3. C) I2 shifted to branch delay slot. D) I1 shifted to branch delay slot and now LABEL pointing to I2.

paarthsinghrathore asked in CO and Architecture Aug 18, 2023

by paarthsinghrathore

345 views

0 votes

1 answer

5

Computer Architecture and Organisation
1. Assume a Bus System constructed to connect 7 registers and memory unit of 32 word length using multiplexer. So: a) How many multiplexer is needed? b) What type of multiplexer is required i.e size of multiplexer? c) Describe decoder used to select address of memory unit

kidussss asked in CO and Architecture Sep 1, 2022

290 views

0 votes

1 answer

6

Question on Pipelining
In a pipeline the maximum ideal speed-up is 5. Let the percentage of unconditional branches in a set of typical program be 5% and that of conditional branches be 10%. If 70% of the conditional branches are taken, calculate % loss of speed-up due to branch instructions. It is very difficult to understand this question and solve it. Please help.

Swarnava Bose asked in CO and Architecture Jul 2, 2022

by Swarnava Bose

1.1k views

0 votes

0 answers

7

NPTEL Assignment Question
Consider the following code : Load R1,M Load R2,N CMP R1,R2 JGE END Store [300],R2 END: Store [300],R1 Assume that M=30 and N=25. The above sequence of instructions is to be executed on a pipelined processor with IF , ... instructions. The branch outcome is known after EX stage. Determine the number of clock cycles required for completion of execution of all instructions.

rsansiya111 asked in CO and Architecture Dec 8, 2021

367 views

3 votes

1 answer

8

How carry and zero flag bits are modified after CMP instruction is executed?
The instruction format is CMP R1, R2. How will the carry and zero flags we be modified after above instruction is executed? Case 1: R1< R2 Carry Flag = 1 Zero Flag = 0 R1= R2 Carry Flag = 0 Zero Flag = 1 R1> R2 ... 0 Zero Flag = 1 R1> R2 Carry Flag = 1 Zero Flag = 0 Which one of the above two cases is correct?

jaswanth431 asked in CO and Architecture Sep 5, 2021

2.1k views

0 votes

1 answer

9

Made Easy
A hypothetical 5 stage processor is designed in which branch is predicted at 3 stage and each stage takes 1 cycle to compute its task. If f is the probability of an instruction being a branch instruction then what is the value of F such that speed up is atleast 3?

anjali007 asked in CO and Architecture Jan 23, 2019

432 views

0 votes

2 answers

10

made easy
A hypothetical 5 stage pipeline processor is designed in which branch is predicted at 3rd stage and each stage takes 1 cycle to compute its tasks. If f is the probability of an instruction being branch instruction then the value of f such that speedup is atleast 3 is____

Harshit Bajpai asked in CO and Architecture Jan 14, 2019

by Harshit Bajpai

1.1k views

0 votes

1 answer

11

How many stall cycles are caused due to each incorrect branch prediction?
The title says it all: How many stall cycles are caused due to each incorrect branch prediction? Additional details you might need: Branch is executed in execution stage of pipeline (but will love to know what happens when branch is executed in decode stage too)

Raj Singh 1 asked in CO and Architecture Jan 9, 2019

753 views

0 votes

1 answer

12

Made easy
Consider a 5 stage pipeline that allows overlapping of all instructions except branch instructions. The target of branch instructions is not available until the branch instruction is completed. Let each stage delay is 20 ns and there are 30% branch instructions. What is the performance gain of pipeline over non-pipeline

Gaurangi Katiyar asked in CO and Architecture Dec 11, 2018

by Gaurangi Katiyar

534 views

1 vote

1 answer

13

Branch Instruction
Assume that the base register contains 32856. The program counter is currently having a value of 25687 memory location. What is the branch address if the address field of jump instruction contains -30 in the address field and instruction is designed with base register addressing mode? 32826 25657 32886 25717

Na462 asked in CO and Architecture Dec 2, 2018

by Na462

506 views

1 vote

0 answers

14

Not a previous year question
Given a non-pipelined architecture running at 1GHz, that takes 5 cycles to finish an instruction. You want to make it pipelined with 5 stages. The increase in hardware forces you to run the machine at 800MHz. The only stalls are caused by ... in 10% of the branch instructions. What is the speedup that can be achieved with pipelining as compared to non-pipelined design?

Cpt.Nemo143 asked in CO and Architecture Nov 17, 2018

1.3k views

1 vote

1 answer

15

made easy test series
What should I assume as the size of HALT instruction ? HALT instruction comes under which type of instruction

amitqy asked in CO and Architecture Nov 15, 2018

by amitqy

1.5k views

0 votes

1 answer

16

Branch Instruction

Na462 asked in CO and Architecture Nov 7, 2018

by Na462

556 views

0 votes

1 answer

17

Test_CO1_Q35
Assume branch instruction occurs 15% of the time and are predicted as not taken, while in practice they are taken 40% of the time with a penalty of 3 cycles. With forwarding, the load delay slot is one cycle and can be filled 60% if the time with useful instructions, 20% of the ... What is the new CPI due to load delay slots and branch hazards? A. 1.204 B. 1.404 C. 2.204 D. 4.404

BOB asked in CO and Architecture Oct 15, 2018

by BOB

262 views

0 votes

1 answer

18

Branch prediction in pipelining part of syllabhs?
Is branch prediction in pipelining im Co and architecture part of gate syllabus?

bts1jimin asked in CO and Architecture Oct 3, 2018

733 views

0 votes

1 answer

19

Branch Offset
Consider a processor where each instruction size is exactly two bytes long. Conditional and unconditional branch instructions use PC relative addressing mode with offset specified in Bytes to the target location of the branch instruction; the offset is always with ... sequence. The below program is executed (All values are specified in decimal), type of memory is byte addressable

Na462 asked in CO and Architecture Sep 24, 2018

by Na462

1.1k views

0 votes

1 answer

20

Pipeline
A computer with a 5 stage pipeline deals with conditional branches by stalling for the next 3 cycle after hitting one. how much does stalling hurt the performance is 20% of all instructions are conditional branches.

Jaggi asked in CO and Architecture Jul 7, 2018

by Jaggi

959 views

3 votes

0 answers

21

Pipeline
Suppose that a computer prefetches upto $20$ instructions in advance. on the average four of these are conditional branches, each with a probability of $90 \%$ of being predict correctly. what is the probability that the prefetching is on the right track?

Jaggi asked in CO and Architecture Jul 7, 2018

by Jaggi

750 views

Page:

Recent questions tagged branch-conditional-instructions