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Recent questions tagged digital-counter
6
votes
2
answers
151
ISRO2007-34
Ring counter is analogous to Toggle Switch Latch Stepping Switch S-R flip flop
go_editor
asked
in
Digital Logic
Jun 10, 2016
by
go_editor
3.5k
views
isro2007
digital-logic
digital-counter
113
votes
20
answers
152
GATE CSE 2016 Set 1 | Question: 8
We want to design a synchronous counter that counts the sequence $0-1-0-2-0-3$ and then repeats. The minimum number of $\text{J-K}$ flip-flops required to implement this counter is _____________.
Sandeep Singh
asked
in
Digital Logic
Feb 12, 2016
by
Sandeep Singh
51.9k
views
gatecse-2016-set1
digital-logic
digital-counter
flip-flop
normal
numerical-answers
6
votes
1
answer
153
MadeEasy Test Series: Digital Logic - Digital Counter
The modulus value of the below asynchronous counter is __________.
Tushar Shinde
asked
in
Digital Logic
Jan 25, 2016
by
Tushar Shinde
1.7k
views
made-easy-test-series
digital-logic
digital-counter
0
votes
2
answers
154
Modulus of counter1.1
Please Explain the inverted clock. How is the first Flip flop getting the Clock input? What Cr(complement) means? And how to judge MSB LSB
Aspi R Osa
asked
in
Digital Logic
Jan 24, 2016
by
Aspi R Osa
534
views
digital-counter
0
votes
1
answer
155
T flipflop counters
What will be the value of G1 and G2 how to calculate them?
Pradip Nichite
asked
in
Digital Logic
Jan 18, 2016
by
Pradip Nichite
387
views
flip-flop
digital-counter
0
votes
1
answer
156
MadeEasy Test Series: Digital Logic - Digital Counter
In figure, initially Q = A = B = 0. After three clock triggers, the states of Q, A and B will be respectively is ___________.
Sandeep Singh
asked
in
Digital Logic
Jan 15, 2016
by
Sandeep Singh
1.4k
views
made-easy-test-series
digital-logic
digital-counter
1
vote
1
answer
157
MadeEasy Test Series: Digital Logic - Digital Counter
The number of Clock pulses needed to change the contents of an 8-bit-up-counter from (10101011) to (00111010) is ______________
Akanksha Kesarwani
asked
in
Digital Logic
Jan 14, 2016
by
Akanksha Kesarwani
1.0k
views
made-easy-test-series
digital-logic
digital-counter
2
votes
1
answer
158
MadeEasy Test Series: Digital Logic - Digital Counter
A binary counter is being pulsed by a 256 KHz clock signal.The output frequency from the MSB flip-flop is 2 KHz. The MOD number is _______ .
Sandeep Singh
asked
in
Digital Logic
Jan 10, 2016
by
Sandeep Singh
3.8k
views
digital-logic
digital-counter
made-easy-test-series
1
vote
2
answers
159
counter
The initial state of a MOD 16 down counter is 0110 . After 37 clock pulses, the state of the counter will be 0001 1011 1101 1010
shreshtha5
asked
in
Digital Logic
Nov 26, 2015
by
shreshtha5
6.0k
views
digital-counter
53
votes
5
answers
160
GATE CSE 1991 | Question: 5-c
Find the maximum clock frequency at which the counter in the figure below can be operated. Assume that the propagation delay through each flip flop and each AND gate is $10\;\text{ns}$. Also, assume that the setup time for the $JK$ inputs of the flip flops is negligible.
ibia
asked
in
Digital Logic
Nov 14, 2015
by
ibia
23.1k
views
gate1991
digital-logic
sequential-circuit
flip-flop
digital-counter
12
votes
3
answers
161
ISRO2015-4
A modulus -$12$ ring counter requires a minimum of $10$ flip-flops $12$ flip-flops $8$ flip-flops $6$ flip-flops
ajit
asked
in
Digital Logic
Oct 12, 2015
by
ajit
10.3k
views
isro2015
digital-logic
digital-counter
0
votes
1
answer
162
Dfa and counter difference?
#digitalelectronics and #deterministicFA please clarify this..... In constructing dfa ,say (num) divisible by 8 or just mod 8 we need minimum of 4 states , 1. So for constructing mod 8 counter we need minimum of states 4(we have to count ... for constructing combi.circuit.... whether my approach is correct ?refer diag 2 3. If there are any other suggestions.. welcomed
Ravi Raaja
asked
in
Digital Logic
Sep 27, 2015
by
Ravi Raaja
574
views
digital-counter
finite-automata
0
votes
2
answers
163
If the initial stage of mod-11 counter is 0110, then what will be the counting sequence for next 24 clock pulses?
Shefali
asked
in
Digital Logic
Sep 22, 2015
by
Shefali
1.1k
views
digital-counter
24
votes
4
answers
164
GATE1992-04-c
Design a $3$-bit counter using D-flip flops such that not more than one flip-flop changes state between any two consecutive states.
Arjun
asked
in
Digital Logic
Sep 22, 2015
by
Arjun
3.3k
views
gate1992
digital-logic
sequential-circuit
flip-flop
digital-counter
normal
descriptive
33
votes
9
answers
165
GATE CSE 1993 | Question: 6-3
For the initial state of $000$, the function performed by the arrangement of the $\text{J-K}$ flip-flops in figure is: Shift Register $\text{Mod- 3}$ Counter $\text{Mod- 6}$ Counter $\text{Mod- 2}$ Counter None of the above
go_editor
asked
in
Digital Logic
Sep 20, 2015
by
go_editor
12.6k
views
gate1993
digital-logic
sequential-circuit
flip-flop
digital-counter
circuit-output
multiple-selects
5
votes
2
answers
166
A cascade of three identical modulo-5 counters has an overall modulus of ?
(A) 5 (B) 25 (C) 125 (D) 625
_Dipak_
asked
in
Digital Logic
Apr 16, 2015
by
_Dipak_
14.9k
views
gate2014ee
digital-logic
digital-counter
52
votes
7
answers
167
GATE CSE 2015 Set 1 | Question: 20
Consider a $4$-bit Johnson counter with an initial value of $0000.$ The counting sequence of this counter is $0, 1, 3, 7, 15, 14, 12, 8, 0$ $0, 1, 3, 5, 7, 9, 11, 13, 15, 0$ $0, 2, 4, 6, 8, 10, 12, 14, 0$ $0, 8, 12, 14, 15, 7, 3, 1, 0$
makhdoom ghaya
asked
in
Digital Logic
Feb 12, 2015
by
makhdoom ghaya
20.7k
views
gatecse-2015-set1
digital-logic
digital-counter
easy
79
votes
8
answers
168
GATE CSE 2015 Set 2 | Question: 7
The minimum number of $\text{JK}$ flip-flops required to construct a synchronous counter with the count sequence $(0, 0, 1, 1, 2, 2, 3, 3, 0, 0, \ldots)$ is _______.
go_editor
asked
in
Digital Logic
Feb 12, 2015
by
go_editor
36.8k
views
gatecse-2015-set2
digital-logic
digital-counter
normal
numerical-answers
28
votes
3
answers
169
GATE IT 2005 | Question: 11
How many pulses are needed to change the contents of a $8$-bit up counter from $10101100$ to $00100111$ (rightmost bit is the LSB)? $134$ $133$ $124$ $123$
Ishrat Jahan
asked
in
Digital Logic
Nov 3, 2014
by
Ishrat Jahan
7.3k
views
gateit-2005
digital-logic
digital-counter
normal
46
votes
3
answers
170
GATE IT 2008 | Question: 37
Consider the following state diagram and its realization by a JK flip flop The combinational circuit generates J and K in terms of x, y and Q. The Boolean expressions for J and K are : $\overline {x \oplus y}$ and $\overline {x \oplus y}$ $\overline {x \oplus y}$ and $ {x \oplus y}$ $ {x \oplus y}$ and $\overline {x \oplus y}$ $ {x \oplus y}$ and $ {x \oplus y}$
Ishrat Jahan
asked
in
Digital Logic
Oct 28, 2014
by
Ishrat Jahan
14.1k
views
gateit-2008
digital-logic
boolean-algebra
normal
digital-counter
25
votes
2
answers
171
GATE CSE 1994 | Question: 11
Find the contents of the flip-flop $Q_2, Q_1$ and $Q_0$ in the circuit of figure, after giving four clock pulses to the clock terminal. Assume $Q_2Q_1Q_0=000$ initially.
Kathleen
asked
in
Digital Logic
Oct 5, 2014
by
Kathleen
5.8k
views
gate1994
digital-logic
sequential-circuit
digital-counter
circuit-output
normal
descriptive
19
votes
1
answer
172
GATE CSE 1994 | Question: 2-1
The number of flip-flops required to construct a binary modulo $N$ counter is __________
Kathleen
asked
in
Digital Logic
Oct 4, 2014
by
Kathleen
6.3k
views
gate1994
digital-logic
sequential-circuit
flip-flop
digital-counter
fill-in-the-blanks
27
votes
6
answers
173
GATE CSE 2011 | Question: 15
The minimum number of $\text{D}$ flip-flops needed to design a mod-258 counter is 9 8 512 258
go_editor
asked
in
Digital Logic
Sep 29, 2014
by
go_editor
15.0k
views
gatecse-2011
digital-logic
normal
digital-counter
52
votes
6
answers
174
GATE CSE 2014 Set 2 | Question: 7
Let $k=2^n$. A circuit is built by giving the output of an $n$-bit binary counter as input to an $n\text{-to-}2^n$ bit decoder. This circuit is equivalent to a $k$-bit binary up counter. $k$-bit binary down counter. $k$--bit ring counter. $k$-bit Johnson counter.
go_editor
asked
in
Digital Logic
Sep 28, 2014
by
go_editor
19.6k
views
gatecse-2014-set2
digital-logic
normal
digital-counter
12
votes
1
answer
175
GATE CSE 2002 | Question: 8
Consider the following circuit. $A = a_2a_1a_0$ and $B=b_2b_1b_0$ are three bit binary numbers input to the circuit. The output is $Z=z_3z_2z_1z_0$. R0, R1 and R2 are registers with loading clock shown. The registers are loaded with their input data with the falling ... b. What does the circuit implement?
Kathleen
asked
in
Digital Logic
Sep 15, 2014
by
Kathleen
3.1k
views
gatecse-2002
digital-logic
normal
descriptive
digital-counter
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