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Recent questions tagged translation-lookaside-buffer
1
vote
1
answer
31
Os TLB question
How they calculated time for number of levels?
muthu kumar
asked
in
Operating System
Dec 16, 2018
by
muthu kumar
1.4k
views
operating-system
translation-lookaside-buffer
paging
0
votes
1
answer
32
MadeEasy Subject Test 2019: Operating System - Translation Lookaside Buffer
A TLB is a hardware device used for speeding up the conversation from virtual address to physical address. Consider a memory management unit where a memory reference takes 500 nanoseconds; TLB (Translation Look aside Buffer) reference ... EMAT using TLB ==> 640ns EMAT wthout TLB ==> 1000ns how to calculate speed Up.?
jatin khachane 1
asked
in
Operating System
Dec 13, 2018
by
jatin khachane 1
883
views
made-easy-test-series
operating-system
translation-lookaside-buffer
0
votes
1
answer
33
TLB OS
Why the formula used here is not P(10) + (1-P)(50) = 20 ?; A computer keeps its page tables in memory. The time required to read a word from the page table is 50ns. To reduce this overhead, the computer has a TLB, which holds 32 (virtual page, physical page frame) pairs and can ... : 10ns + (1 - p) 50ns = 20ns p =4/5 = .80 The TLB hit rate has to be 80% for a mean access time of 20ns.
rahuljai
asked
in
Operating System
Dec 3, 2018
by
rahuljai
1.3k
views
translation-lookaside-buffer
operating-system
hit-ratio
paging
virtual-memory
0
votes
1
answer
34
ace test series
A computer whose processes have 1024 pages in their address spaces keeps its page tables in memory. The overhead required for reading a word from the page table is 500 nsec. To reduce this overhead, the computer has tlb which holds 32 entries and can do look up in 100 nsec. What hit rate is needed to reduce the mean overhead to 200 nsec? can anyone solve this
vijju532
asked
in
Operating System
Nov 28, 2018
by
vijju532
777
views
operating-system
translation-lookaside-buffer
paging
0
votes
0
answers
35
TLB Effective Access Time
Balaji Jegan
asked
in
Operating System
Nov 27, 2018
by
Balaji Jegan
1.5k
views
operating-system
translation-lookaside-buffer
effective-access-time
numerical-answers
0
votes
0
answers
36
raman classes test series
.. an getting 0.00010650
Gate Fever
asked
in
Operating System
Nov 13, 2018
by
Gate Fever
341
views
operating-system
paging
translation-lookaside-buffer
raman-classes-test-series
numerical-answers
0
votes
0
answers
37
SudoGate Test Series - Virtual Memory
A computer system has TLB access time = 30 ns and the main memory access time is 150 ns and if the miss rate is 20 % the calculate the effective memory access time if 3 level of paging is applied. i am getting 270 ns
Gurdeep Saini
asked
in
Operating System
Nov 5, 2018
by
Gurdeep Saini
611
views
operating-system
translation-lookaside-buffer
virtual-memory
0
votes
2
answers
38
Memory overhead in Multilevel paging with TLB
Consider a computer system using 2-level paging with TLB.The logical address supported is 32 bits.The page table is divided into 512 pages each of size 1K.The memory access time is 100ns and the TLB access time 15ns .Page table entry size at 1st ... page table along with the page of the second level page table for a process? A)6KB B)4KB C)5KB D)12KB
Deepanshu
asked
in
Operating System
Oct 1, 2018
by
Deepanshu
1.7k
views
multilevel-paging
paging
translation-lookaside-buffer
1
vote
2
answers
39
Virtual Memory
Which of the following is true? A. If the page size increases page fault rate may also increase. B. Multi-level paging optimizes program execution time. C. Dynamic linking increases program execution time.Correct Option D. TLB is a software data structure.
Na462
asked
in
Operating System
Jul 18, 2018
by
Na462
1.7k
views
virtual-memory
operating-system
memory-management
paging
translation-lookaside-buffer
0
votes
0
answers
40
caching and virtual memory
I am having troble with these following questions. Please I need help
Samson Bankole
asked
in
Operating System
Apr 19, 2018
by
Samson Bankole
377
views
virtual-memory
operating-system
cache-memory
translation-lookaside-buffer
2
votes
0
answers
41
Does every process have its own TLB?
I know that every process has its own page table and but is it the same with TLB? Does every process have its own TLB or there is a master TLB which is used by all the processes?
punkprincess
asked
in
Operating System
Apr 5, 2018
by
punkprincess
3.1k
views
translation-lookaside-buffer
2
votes
1
answer
42
My doubt on TLB and page fault
First read this whole thing what I am writing below: Case 1: If we have to access unit address in memory using TLB and we assume that no page fault occurs then, EMAT=p( T+M )+( 1-p ) (T+M+M) T=TLB access time, M= ... if there page fault occurs then how does the last calculated EMAT here affects the first Estimated memory access time which we have calculated using TLB?
Akash Kumar Roy
asked
in
Operating System
Apr 5, 2018
by
Akash Kumar Roy
2.6k
views
operating-system
translation-lookaside-buffer
hit-ratio
page-fault
effective-memory-access
0
votes
0
answers
43
TLB JUST FOR KNOWLEDGE
TLB IS EITHER HARDWARE OR SOFTWARE PLZ EXPLAIN BRIEFLY?????
Sunidhi chauhan
asked
in
CO and Architecture
Dec 16, 2017
by
Sunidhi chauhan
408
views
translation-lookaside-buffer
0
votes
0
answers
44
OS TLB
compute system implement a 36-bit virtual address page size of 16KB and a 256-entry translation look aside buffer organized into 64 sets each having four ways.assume that the TLB tag does not store any process id. the minium length of the TLB tag in bits is?
Akshay Koli 4
asked
in
Operating System
Dec 12, 2017
by
Akshay Koli 4
517
views
translation-lookaside-buffer
operating-system
3
votes
1
answer
45
TLB buffer
My doubt is Sorry if its silly. 1. TLB Maps from VA --> PA, so when its accessed ? is it when cpu generates logical address and by hardware it get convert into virtual address and then tlb is looked to convert into physical address. 2. When a ... Virtual address space to physical address space i.e. TLB Stores frequent mapping of pages. So where is actually TLB Stored is it in cache?
Na462
asked
in
CO and Architecture
Nov 26, 2017
by
Na462
1.0k
views
translation-lookaside-buffer
virtual-memory
0
votes
0
answers
46
Effective memory access time
please explain how to understand this problem
Parshu gate
asked
in
CO and Architecture
Nov 20, 2017
by
Parshu gate
2.5k
views
effective-memory-access
co-and-architecture
translation-lookaside-buffer
2
votes
2
answers
47
TLB HITS
What is the average memory access time (correct to two decimal places) when you have the following memory hierarchy? Assume that (i) the cache uses physical addresses, (ii) the CPU stalls until the data is delivered, (iii) everything fits into the memory, and (iv) the hardware does the page table walk and updates TLB.
Parshu gate
asked
in
Databases
Nov 11, 2017
by
Parshu gate
678
views
translation-lookaside-buffer
hit-ratio
co-and-architecture
cache-memory
4
votes
1
answer
48
Virtual Memory
Shivam Chauhan
asked
in
Operating System
Oct 25, 2017
by
Shivam Chauhan
946
views
operating-system
translation-lookaside-buffer
virtual-memory
3
votes
0
answers
49
Effective memory access time
What has to be the general and final formula for calculating the effective memory access time, taking in consideration the $\alpha$-level page table, TLB hit ratio as $h$, miss ratio as $m$, memory access time as $M$ ... for page fault servicing as $x$? There seems to be so many formulae, each different from each other depending on the question.
habedo007
asked
in
CO and Architecture
Aug 17, 2017
by
habedo007
1.0k
views
co-and-architecture
effective-memory-access
translation-lookaside-buffer
operating-system
5
votes
1
answer
50
Multilevel TLB performance
A computer has a 128-entry $L_1$ TLB, 1024-entry $L_2$ TLB, and uses page size of 4KB. A program reads a 1MB array, one byte at a time from start to end, 10 times. Assuming the TLBs are directly mapped and initially empty, and no other memory is accessed, find TLB hits and misses of both $L_1$ and $L_2$ TLB (array is page aligned).
habedo007
asked
in
Operating System
Aug 8, 2017
by
habedo007
953
views
operating-system
translation-lookaside-buffer
paging
hit-ratio
5
votes
1
answer
51
Self-doubt
Can there ever be a TLB hit and a page fault?
just_bhavana
asked
in
Operating System
Jul 23, 2017
by
just_bhavana
1.4k
views
operating-system
translation-lookaside-buffer
1
vote
2
answers
52
Test by Bikram | Mock GATE | Test 2 | Question: 15
A certain computer has a $TLB$ cache, a one-level physically-addressed data cache, $DRAM$, and a disk backing store for virtual memory. The processor loads the instruction below and then begins to execute it. LW R3, 0(R4) $[$ LW ... one data cache miss can occur. If a page fault occurs, then a data cache miss definitely does not occur as well.
Bikram
asked
in
GATE
Jan 24, 2017
by
Bikram
758
views
tbb-mockgate-2
co-and-architecture
cache-memory
translation-lookaside-buffer
1
vote
0
answers
53
tlb segmentation paging
Consider a memory system consists of a single external cache with an access time of 30ns and a hit rate of 0.85, and a main memory with an access time of 80ns. Now we add virtual memory to the system. The TLB is implemented internal to the processor chip and takes ... memory access time of the system with virtual memory?( Marks: 0.00 ) 8ns 30ns 40ns 51ns
Neal Caffery
asked
in
Operating System
Jan 17, 2017
by
Neal Caffery
905
views
operating-system
paging
translation-lookaside-buffer
hit-ratio
1
vote
3
answers
54
TLB paging
Consider a system with 2-levels of paging and a TLB with hit rate of 95% and TLB access time of 1ns. Find the effective memory access time if there’s a data cache whose hit rate is 85% and cache access time is 1ns, and main memory access time is 100ns. 100ns. 27ns 25ns 30ns 20ns
Neal Caffery
asked
in
Operating System
Jan 17, 2017
by
Neal Caffery
3.7k
views
operating-system
translation-lookaside-buffer
paging
hit-ratio
6
votes
2
answers
55
TLB and paging
Consider the following piece of code which multiplies two matrices: int a[1024][1024], b[1024][1024], c[1024][1024]; multiply() { unsigned i, j, k; for(i = 0; i < 1024; i++) for(j = 0; j < 1024; j++) for(k = 0; k < ... requires 4 bytes for storage. Compute the number of TLB misses if the page size is 4096 and the TLB has 8 entries with a replacement policy consisting of LRU.
sushmita
asked
in
Operating System
Jan 5, 2017
by
sushmita
1.1k
views
operating-system
translation-lookaside-buffer
paging
1
vote
1
answer
56
Computing Effective Memory access time - Cache organization
Consider the following information about a hypothetical processor. Assume the cache is physically addressed TLBHit Rate: 95% access time 1 cycle Cache Hit Rate: 90% access time 1 cycle when tlb and cache both get miss, page fault rate 1% TLB access and ... 1 + .1(5+ .01(100) ) = 2.675 Could someone pls point out the flaw in the logic?
yg92
asked
in
CO and Architecture
Dec 26, 2016
by
yg92
1.3k
views
co-and-architecture
cache-memory
translation-lookaside-buffer
0
votes
0
answers
57
TLB concept
As cache is divided into no of blocks same as physical address space... Does the TLB is also divided..??
vaishali jhalani
asked
in
Operating System
Dec 21, 2016
by
vaishali jhalani
580
views
translation-lookaside-buffer
9
votes
1
answer
58
virtually/physically tagged caches
can some one please clearly explain ,what is 1. virtually indexed virtually tagged cache 2. physically indexed physically tagged cache 3. virtually indexed physicaly tagged cache it is very confusing ,these concepts are used in finding effective memory access in questions of gate.
Akriti sood
asked
in
CO and Architecture
Nov 9, 2016
by
Akriti sood
3.6k
views
co-and-architecture
cache-memory
virtual-memory
translation-lookaside-buffer
2
votes
3
answers
59
TLB hit ratio
Consider a paging system uses, TLB’s access time is 30 ns and memory access time is 200ns. If the effective memory access time is 150ns, what will be the hit ratio of TLB?
Veerendra V
asked
in
Operating System
Nov 8, 2016
by
Veerendra V
6.8k
views
translation-lookaside-buffer
hit-ratio
virtual-memory
2
votes
2
answers
60
Virtually indexed caches
What is virtual indexed cache? How is it different from physical indexed cache? What is virtually indexed physical tagged cache? If possible point me to proper resources.
Veerendra V
asked
in
Operating System
Nov 6, 2016
by
Veerendra V
1.6k
views
cache-memory
multilevel-cache
co-and-architecture
virtual-memory
translation-lookaside-buffer
operating-system
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