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User Sunil8860
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Recent activity by Sunil8860
3
answers
1
breadth first search
The max possible height of BFS tree , if BFS is run on a complete bipartite graph Km,n where m>=1 , n>=1 with starting vertex S is
commented
in
Programming in C
Sep 22, 2017
2.7k
views
breadth-first-search
bipartite-graph
0
answers
2
program output
asked
in
Programming in C
Sep 21, 2017
372
views
programming-in-c
bad-question
1
answer
3
Virtual GATE test series
commented
in
Computer Networks
Sep 19, 2017
604
views
application-layer-protocols
1
answer
4
cogestion window
asked
in
Computer Networks
Sep 19, 2017
279
views
congestion-control
1
answer
5
test series
In a IPv6 protocol communication, If total Router Header length is 448 bits. Then how many routers or hops are there for the packet to reach destination. 3 4 5 2
commented
in
Computer Networks
Sep 18, 2017
1.0k
views
1
answer
6
fragmentation
The following IPv4 header, shown in hex below, is received for an IP packet at its destination. 4500 003c 1c46 4000 4017 c311 aca8 0101 aca8 0102 Using the Internet checksum algorithm, determine if there were any errors in the transmission?: Single bit error Double bit error More than 2 bit error No error
commented
in
Computer Networks
Sep 17, 2017
766
views
computer-networks
4
answers
7
GATE IT 2008 | Question: 67
Two popular routing algorithms are Distance Vector(DV) and Link State (LS) routing. Which of the following are true? (S1): Count to infinity is a problem only with DV and not LS routing (S2): In LS, the shortest path algorithm is run only at one node ( ... lesser number of network messages than LS S1, S2 and S4 only S1, S3 and S4 only S2 and S3 only S1 and S4 only
commented
in
Computer Networks
Sep 16, 2017
9.6k
views
gateit-2008
computer-networks
routing
normal
1
answer
8
split horizon
suppose C-D link is broken then what will be the vector of D instantaneously ??
asked
in
Computer Networks
Sep 16, 2017
618
views
split-horizon
distance-vector-routing
4
answers
9
GATE CSE 2014 Set 2 | Question: 25
In the diagram shown below, $L1$ is an Ethernet LAN and $L2$ is a Token-Ring LAN. An $IP$ packet originates from sender $S$ and traverses to $R$, as shown. The links within each $\text{ISP}$ and across the two $\text{ISP}$s, are all ... $\text{TTL}$ field is $32$. The maximum possible value of the $\text{TTL}$ field when $R$ receives the datagram is _______.
commented
in
Computer Networks
Sep 6, 2017
18.0k
views
gatecse-2014-set2
computer-networks
numerical-answers
lan-technologies
ethernet
token-ring
normal
1
answer
10
doubts
The Token Bucket is filled at rate of 2 Mbps. Is this means that after one second 2Mb of data will be available at the bucket ready to be sent to the network ? what about the number of token produced?
asked
in
Computer Networks
Sep 5, 2017
530
views
computer-networks
token-bucket
0
answers
11
turing machine and language
asked
in
Theory of Computation
Sep 4, 2017
235
views
turing-machine
1
answer
12
decidability
asked
in
Theory of Computation
Sep 4, 2017
408
views
theory-of-computation
decidability
0
answers
13
languages
asked
in
Theory of Computation
Sep 4, 2017
204
views
theory-of-computation
regular-language
context-free-language
0
answers
14
context free grammer
asked
in
Theory of Computation
Sep 4, 2017
230
views
regular
expression
2
answers
15
regular expression
asked
in
Theory of Computation
Sep 4, 2017
803
views
regular
expression
1
answer
16
doubts
I am not getting the question
asked
in
Theory of Computation
Sep 4, 2017
283
views
theory-of-computation
0
answers
17
set-up time of flip flop
what is meant by set up time in this question?
asked
in
Digital Logic
Aug 31, 2017
161
views
digital-logic
1
answer
18
adder
This is binary to radix -12 circuit, how?
asked
in
Digital Logic
Aug 30, 2017
661
views
digital-logic
adder
0
answers
19
waveforms
Que:- You are given a free running clock with a duty cycle of 50% and a digital waveform f which changes only at the negative edge of the clock. Which one of the following circuits (using clocked D flip-flops) will delay the phase of f by 180°? I don't get what is duty cycle of 50% means and and what is meant by delay the phase by 180?
asked
in
Digital Logic
Aug 29, 2017
325
views
digital-logic
2
answers
20
gate 2014
which is faster, synchronous circuits or asynchronous circuits and why?
commented
in
Digital Logic
Aug 29, 2017
1.3k
views
digital-logic
synchronous-asynchronous-circuits
asynchronous-circuit
1
answer
21
DECIDABILITY
Is complement of language same type or not decidable by CFL and recursive language or not??? Grammar is ambiguous or not? Grammar in regular/CFL/rel decidable or not?
answered
in
Theory of Computation
Aug 16, 2017
1.4k
views
decidability
theory-of-computation
turing-machine
recursive-and-recursively-enumerable-languages
context-free-language
bad-question
2
answers
22
Decidability
True/False? The complement of every Turning decidable language is Turning decidable
asked
in
Theory of Computation
Aug 16, 2017
757
views
theory-of-computation
decidability
0
answers
23
Doubt
Suppose there are two FA's F1 and F2 and given that L(F1) = L(F2) then it means F1 and F2 are same .
asked
in
CO and Architecture
Aug 16, 2017
343
views
theory-of-computation
finite-automata
regular-language
0
answers
24
Context free language
Consider the NPDA 〈Q = {q0, q1, q2}, Σ = {0, 1}, Γ = {0, 1, ⊥}, δ, q0, ⊥, F = {q2}〉, where (as per usual convention) Q is the set of states, Σ is the input alphabet, Γ is stack alphabet, δ is the state transition ... : Which one of the following sequences must follow the string 101100 so that the overall string is accepted by the automaton? A 10110 B 10010 C 01010 D 01001
asked
in
Theory of Computation
Aug 16, 2017
557
views
theory-of-computation
context-free-language
1
answer
25
Closure
Context-free grammar is closed over intersection true/false.
asked
in
CO and Architecture
Aug 16, 2017
311
views
theory-of-computation
closure-property
5
answers
26
GATE CSE 2016 Set 1 | Question: 44
Let $X$ be a recursive language and $Y$ be a recursively enumerable but not recursive language. Let $W$ and $Z$ be two languages such that $\overline{Y}$ reduces to $W$, and $Z$ reduces to $\overline{X}$ (reduction means the standard ... enumerable. $W$ is not recursively enumerable and $Z$ is recursive. $W$ is not recursively enumerable and $Z$ is not recursive.
commented
in
Theory of Computation
Aug 15, 2017
12.4k
views
gatecse-2016-set1
theory-of-computation
easy
recursive-and-recursively-enumerable-languages
reduction
1
answer
27
status Register & I/o
What is the work of status register in I/O operation ?
commented
in
CO and Architecture
Aug 15, 2017
1.5k
views
co-and-architecture
io-handling
registers
1
answer
28
doubt
what is the RE of the above DFA?
asked
in
Theory of Computation
Aug 15, 2017
451
views
theory-of-computation
finite-automata
regular-expression
6
answers
29
GATE CSE 2013 | Question: 17
Which of the following statements is/are FALSE? For every non-deterministic Turing machine, there exists an equivalent deterministic Turing machine. Turing recognizable languages are closed under union and complementation. Turing decidable languages are closed under intersection and ... and intersection. $1$ and $4$ only $1$ and $3$ only $2$ only $3$ only
answer selected
in
Theory of Computation
Aug 15, 2017
20.9k
views
gatecse-2013
theory-of-computation
normal
closure-property
0
answers
30
geeksforgeeks
L1 is a recursively enumerable language over Σ. An algorithm A effectively enumerates its words as w1, w2, w3, … Define another language L2 over Σ Union {#} as {wi # wj : wi, wj ∈ L1, i < j}. Here # is a new symbol. Consider the following assertions. S1 : L1 is recursive implies L2 is recursive S1 is correct can anyone explain how?
asked
in
Theory of Computation
Aug 14, 2017
351
views
theory-of-computation
recursive-and-recursively-enumerable-languages
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