GATE CSE 2004 | Question: 18, ISRO2007-31

Question

In an $SR$ latch made by cross-coupling two NAND gates, if both $S$ and $R$ inputs are set to $0$, then it will result in

• A. $Q = 0, Q' = 1$
• B. $Q = 1, Q' = 0$
• C. $Q = 1, Q' = 1$
• D. Indeterminate states

Comments

(C) is the correct answer!

~Source: Morris Mano

---

Can you upload this pdf somewhere and share link please?

---

https://cs.ccsu.edu/~markov/ccsu_courses/ch05-pdf.pdf

Page 3-4

 

---

​​​​​​A good watch!

Answer 1

Answer should be C. The reasoning is as follows:

When both $R$ and $S$ are set as $0,$ we will get both $Q$ and $Q'$ as $1$ (these must be ideally mutually complementary).  This output will be permanent and is not dependent on any sequence of events but just the input values (so no race condition). But after this state if we enter both $R$ and S as $1,$ the output will be indeterminate depending on which NAND gate processes first (either $Q$ or $Q'$ will become $0$  but we can't determine which (race condition) and it will lead to an indeterminate state.

PS: $R = 0, S = 0$ in an SR latch made by cross coupling $2$ NAND gates will lead to a forbidden state. Forbidden state means, this state is invalid and must not be entered. This is different from an indeterminate state which means a state where we are not sure of the output. Again this is different from a toggling state where the output changes continuously.

Comments

But , in latch , we have no control on the inputs since clock is not used in latch and we can't enter the inputs as our wish . The inputs will be some arbitrary external input through other parts of the circuit, which can be changing any time. so, it will not remain in (1,1) state, instead the state will become indeterminate.

---

The output will definetely fluctuate and becomes indeterminate.

---

beautifully explained.

Answer 2

If both R =0 ,S=0 ,then both Q and Q’ tend to be ‘1’. NAND gate says if both inputs are 1,the output is 0. The logic of the circuit (Q’ is complement of Q) not satisfied, Logic state is said to be indeterminate state or racing state. Each state, Q =‘1’and Q =‘0’, and Q =‘0’, Q=‘1’ trying to race through so “RACE CONDITION” occurs and output become unstable. So ans is (D).

Comments

Yes. isn't it SR latch ? If so what it is called then ! Confused !!

---

An SR latch (Set/Reset) is an asynchronous device: it works independently of control signals and relies only on the state of the S and R inputs. In the image we can see that an SR latch can be created with two NOR gates that have a cross-feedback loop. SR latches can also be made from NAND gates, but the inputs are swapped and negated. In this case, it is sometimes called an SR latch.

Ref::https://en.wikibooks.org/wiki/Digital_Circuits/Latches

---

Does anybody know the answer given in GATE keys? I think there's still confusion between option C and D.

Answer 3

invalid state mentioned here is indeterminate state,

what happens in indeterminate state is output keeps of changing between 0 and 1 infinitely

so we can not anything in latch or not decide what is stored in latch thats why the name indeterminate state.

If you want to prove to yourself how latch goes to invalid state, draw diagram,  draw truth table, apply input and see it going infinitely

Answer 4

Answer: D

Q and Q' will come as 1 each which is an indeterminate state as the outputs are not complementary.

http://en.wikipedia.org/wiki/Flip-flop_(electronics)

Comments

then why not option c too ??

---

isn't it a invalid state,

explain ??

---

https://en.wikibooks.org/wiki/Digital_Circuits/Latches