GATE CSE 2017 Set 1 | Question: 25

Question

Consider a two-level cache hierarchy with $L1$ and $L2$ caches. An application incurs $1.4$ memory accesses per instruction on average. For this application, the miss rate of $L1$ cache is $0.1$; the $L2$ cache experiences, on average, $7$ misses per $1000$ instructions. The miss rate of $L2$ expressed correct to two decimal places is ________.

Comments

https://stackoverflow.com/questions/34215343/is-local-miss-rate-equivalent-to-the-global-miss-rate-for-the-lowest-level-of-a

https://gatestack.in/t/local-and-global-cache-miss-rate/499

 

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answer is 0.05

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Hope this helps.

Answer 1

Answer = $0.05$.

Assuming there are 1000 instructions for the ease of calculation, which means there are 7 memory reference misses from the L2 cache.

A cache experiences misses with memory references. Thus, it is essential to determine the counts of incoming memory references and the counts of memory references hitting or missing in order to calculate the cache hit rate or miss rate. Upon reading the question, it becomes apparent that the incoming memory references to the L2 cache are unknown, and we must derive this information using the provided L1 cache information.

 

 

Comments

how 1000 instructions from cpu to L1 ??

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Actually is the 1400 Mem access request to L1 . I have showed 1000 instruction as in the question.

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I M NOT getting .... 1.4 mem ref was given u hv done 1400... i m not getting anything..

OK...i got 1000* 1.4 = 1400

but then from L1 to L2  .. how 140 ???

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• An application incurs 1.4 memory accesses per instruction on average & Total instruction are 1000 so total number of memory references = 1.4 * 1000 = 1400
• The miss rate of L1 cache is 0.1  i.e. out of 1400 ,0.1% miss so 1400* 0.1= 140
•  the L2 cache experiences, on average, 7 misses out of 140 miss in cache L1 = 7/140 = 0.05.

1. Note since we are moving toward main memory and secondary memory miss rate is decreases.
2. Miss rate =  number of misses /total number of accesses

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Ans is 0.05 and not 0.5 ,right?

@Debashish

miss rate of L2 means, miss rate of L2 instruction w.r.t total instruction in L1 or total instruction in main memory?

As it is given miss rate w.r.t 1000 instruction and u r calculating miss rate w. r. t L1 cache instruction

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because only 0.1*1400 = 140 will reach to L2. Because miss rate of L1 is 0.1.

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Why we are not making it as 7/1000 as 7 inst are missing out of 1000

So , out of 140 instruction

 (7/1000)*140.

Please advise.

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Hello krishna

140 are not instructions , they are #of memory accesses.Convert 1000 instructions into # of memory accesses for $L_{2}$ cache , $L_{2}$ cache will only be accesses when there is a miss case for $L_{1}$ cache.

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@Krishna 1000 instructions are there out of which total number of memory reference = 1000 * 1.4 = 1400

Now 1400 L1 have miss rate of 0.1 so

reference to l2 cache = .1 * 1400 = 140.  That is 140 instructions are referring L2 cache out of which 7 are miss.

now miss rate = 7/140 = .05

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The answer is 0.05 not 0.5...

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in question given .... 7 misses per 1000 instructions 

my doubt is....... how do you know that these 7 are memory references misses ?

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When there is a  memory reference then definitely cache memory is accessed first.. If the word is not present in the cache then it is definitely the case of cache miss...

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They are asking Local Miss rate of $L_2$. The Global miss rate for $L_2$=0.005

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please explain how will we calculate global miss rate

is it 7/1000

and why 0.005

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GMR(L2)=7/1400

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@vijay kumar 2

Local miss rate=number of misses in a cache divided by number of accesses to that cache

Global miss rate=number of misses in a cache divided by number of memor accesses generated by the processor

For L1 cache, global miss rate=local miss rate.

For L2 cache, global miss rate=Local miss rate of L1 ×Local miss rate of L2

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Hi Shweta, it is given in the question that we have 1000 instructions

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@stoneheart don’t you think this is very ambiguous per 1000 inst, I by default assumed they said it for L2 cache that 7 miss per 1000 instruction so I solved like this, say we have 100 inst then 10 will sent to L2 and then 10*7/1000 would be miss in there so globally .07/100 will be miss rate

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thanks

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Note:

Most of the time Miss rate is always based on number of memory references…

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@dd  thanks 🙏

Answer 2

Best explanation found

Since , it is given in question that for 1 instruction it takes 1.4 memory access(ma)

So, for 1000 instr. it will take =1000* 1.4 ma= 1400 ma

Now , it is given for l1 cache miss rate(mr) = 0.1

and since , we know mr=no. of misses/total no. of ma

so, 0.1=no. of misses/1400

thus, no. of misses of l1 =140

As , we know when there is miss in l1 , we search for data in l2

so, now for l2 cache total no. of ma=140, and it is given there is 7 miss

so , mr for l2 cache=7/140=1/20=0.05

Comments

As , we know when there is miss in l1 , we search for data in l2

Thank you. This clearified my doubt :)

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@Shamim Ahmed

Welcome

Answer 3

total number of memory reference = 1000 * 1.4 = 1400

reference to l2 cache = .1 * 1400 = 140

now miss rate = 7/140 = .05

Answer 4

I really think that for an exam as prestigious as GATE, this question is worded very poorly.

the L2 cache experiences, on average, 7 misses per 1000 instructions. The miss rate of L2 expressed correct to two decimal places is ....

One can argue that it is 7/1000 = 0.007

I.e. per 1000 instructions given to L2, it misses 7 of them.

But the question actually says, per 1000 instructions given to L1, L2 ultimately misses 7 of them.

 

So, give L1 1000 instructions

=> 1400 memory accesses

=> Missed 140 memory accesses.

 

These 140 accesses would pe passed through L2 because of the hierarchy, and L2 would miss 7 of them.

So miss rate of L2 = 7/140 = 0.05.

 

PS: If 0.05 wasn't in the official answer key, I'd never have believed it to be the answer. One of the rare poorly worded GATE question.

Comments

your answers always make more sense to me. Thanks buddy.

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Thanks for this “But the question actually says, per 1000 instructions given to L1, L2 ultimately misses 7 of them”. :)

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Where that line is written?