Best explanation found
Since , it is given in question that for 1 instruction it takes 1.4 memory access(ma)
So, for 1000 instr. it will take =1000* 1.4 ma= 1400 ma
Now , it is given for l1 cache miss rate(mr) = 0.1
and since , we know mr=no. of misses/total no. of ma
so, 0.1=no. of misses/1400
thus, no. of misses of l1 =140
As , we know when there is miss in l1 , we search for data in l2
so, now for l2 cache total no. of ma=140, and it is given there is 7 miss
so , mr for l2 cache=7/140=1/20=0.05