$L2$ cache is shared between Instruction and Data (is it always? see below)
So, average read time
$=$ Fraction of Instruction Fetch $\ast $ Average Instruction fetch time $+$ Fraction of Data Fetch $\ast$ Average Data Fetch Time
Average Instruction fetch Time $= L1$ access time $+ L1$ miss rate $\ast \;L2$ access time $+ L1$ miss rate $\ast\; L2$ miss rate $\ast $ Memory access time
$\quad= 2 + 0.2 \times 8 + 0.2 \times 0.1 \times 90$
$\quad= 5.4 \;\text{ns}$
Average Data fetch Time $= L1$ access time $+ L1$ miss rate $\ast \;L2$ access time $+ L1$ miss rate $\ast \;L2$ miss rate $\ast $ Memory access time
$\quad = 2 + 0.1 \times 8 + 0.1 \times 0.1 \times 90$
$\quad= 3.7\;\text{ns}$
So, average memory access time
$$= 0.6 \times 5.4 + 0.4 \times 3.7 = 4.72\; \text{ns}$$
Now, why $L2$ must be shared? Because we can otherwise use it for either Instruction or Data and it is not logical to use it for only $1.$ Ideally this should have been mentioned in question, but this can be safely assumed also (not enough merit for Marks to All). Some more points in the question:
Assume that the caches use the referred-word-first read policy and the writeback policy
Writeback policy is irrelevant for solving the given question as we do not care for writes. Referred-word-first read policy means there is no extra time required to get the requested word from the fetched cache line.
Assume that all the caches are direct mapped caches.
Not really relevant as average access times are given
Assume that the dirty bit is always 0 for all the blocks in the caches
Dirty bits are for cache replacement- which is not asked in the given question. But this can mean that there is no more delay when there is a read miss in the cache leading to a possible cache line replacement. (In a write-back cache when a cache line is replaced, if it is dirty then it must be written back to main memory).
