GATE CSE 1998 | Question: 1.20

Question

Which of the following is true?

• A. Unless enabled, a CPU will not be able to process interrupts.

• B. Loop instructions cannot be interrupted till they complete.

• C. A processor checks for interrupts before executing a new instruction.

• D. Only level triggered interrupts are possible on microprocessors.

Comments

The (C) is false as shown in the below screenshot:

Interrupt check happens before the CPU fetches new instruction.

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What about piplelined processors? The fetching cannot wait.

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Divy Kala

there also it should check.

Answer 1

Answer is (A).

Options (B) and (D) are obviously false.

A processor checks for the interrupt before FETCHING an instruction, so option (C) is also false.

Comments

This might seem funny but i took the ‘enabling’ in option A to be of the CPU itself and not the interrupts. Can the option A mean this?

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Fetching comes before execution → checks for interrupts “before execution” → checks for interrupts before “decoding” ..so on
So in a MSQ sence opt (C) is also right

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@KartikGawande obviously yess bro , because if the CPU is disabled then how will the interuppt even be processed.

Answer 2

are both option (a) and (c)  TRUE .... explain ???
Option (c) “Polling is like picking up your phone every few seconds to see if you have a call. Interrupts are like waiting for the phone to ring.”

CPU senses (checks) interrupt request line after every instruction; if raised,.... correct me

http://www.cs.toronto.edu/~demke/469F.06/Lectures/Lecture6.pdf or archive

Comments

@Swami Patil

Option C is wrong because we know that instruction has to pass through various phases(fetching, decoding, executing, writeback ), after completion of instruction CPU has to check for interrupts.

CPU can not check interrupts after executing phase..

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Why are we assuming it to be a pipelined system?

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Anybody with this toronto pdf? It's saying forbidden