GATE CSE 1998 | Question: 1.20

Question

Which of the following is true?

• A. Unless enabled, a CPU will not be able to process interrupts.

• B. Loop instructions cannot be interrupted till they complete.

• C. A processor checks for interrupts before executing a new instruction.

• D. Only level triggered interrupts are possible on microprocessors.

Comments

The (C) is false as shown in the below screenshot:

Interrupt check happens before the CPU fetches new instruction.

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What about piplelined processors? The fetching cannot wait.

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Divy Kala

there also it should check.

Answer 1

Answer is (A).

Options (B) and (D) are obviously false.

A processor checks for the interrupt before FETCHING an instruction, so option (C) is also false.

Comments

This might seem funny but i took the ‘enabling’ in option A to be of the CPU itself and not the interrupts. Can the option A mean this?

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Fetching comes before execution → checks for interrupts “before execution” → checks for interrupts before “decoding” ..so on
So in a MSQ sence opt (C) is also right

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@KartikGawande obviously yess bro , because if the CPU is disabled then how will the interuppt even be processed.

Answer 2

are both option (a) and (c)  TRUE .... explain ???
Option (c) “Polling is like picking up your phone every few seconds to see if you have a call. Interrupts are like waiting for the phone to ring.”

CPU senses (checks) interrupt request line after every instruction; if raised,.... correct me

http://www.cs.toronto.edu/~demke/469F.06/Lectures/Lecture6.pdf or archive

Comments

Suppose one wants to know who is the Prime Minister of Australia. If he asks this to someone we say "he enquired about Australian Prime Minister". Now, if someone tells him this info without asking, still he needs to open his ear and listen to it. But we never say "he enquired" here.

In similar way, (c) is wrong :) In very concrete sense it is correct. But we have to be at the right level of abstraction- when someone asks what happens inside CPU we shouldn't say 0's and 1's interchange each other ;)

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:) yes , funtastic
he can't find way, ,  but thank you :) ,
instruction cycle with interrupt is the last stage of instruction cycle , so it should perform instruction execution ..steps
1) instruction fetch
2) instruction execution

then
3) interrupt checking
if interrupt is present there then interrupt service else aglo is repeat 1 then 2 ..... so on

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I wouldn't call the 3 a step. Interrupt line is checked at that time, but it is not having any overhead.

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ans is only A here then?

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yes..

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Arjun sir, how?

enabling is for software and user generated interrupts only right?

for hardware interrupts e.g. system failures also do we need the enabling?

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I think they meant only maskable interrupts. Thermal interrupt will be always enabled, right?

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please comment about loop instruction point, I understand that if loop instructions cannot be interrupted then infinite loops may result. But is this correct reasoning for this option to be false? Can you please give me some more details? Or should I go and read some good book on microprocessors too. I read Douglas Hall for 8086 in my college days, just want to avoid that now. How exactly loop instructions are processed?

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Sir I. Am not getting why option c is wrong

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@Swami Patil

Option C is wrong because we know that instruction has to pass through various phases(fetching, decoding, executing, writeback ), after completion of instruction CPU has to check for interrupts.

CPU can not check interrupts after executing phase..

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Why are we assuming it to be a pipelined system?

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Anybody with this toronto pdf? It's saying forbidden