MadeEasy Subject Test: CO & Architecture - Pipelining

Question

Which of the following statements are true?

1. WAW and WAR can be reduced but cannot be completely removed from the pipeline.

2.In direct mapped cache,may produce more misses of program refers to a memory word that occupies same tag value

3.By register renaming,all the stalls created by anti data dependency are eliminated

Comments

The question sentence is very poorly framed.

Answer 1

If we see statement 1 and statement 3 , they are mutually exclusive statements..

Using the technique known as register renaming , all WAR and WAW hazards can be eliminated totally not simply mitigated only..Hence statement 1 is false while statement 3 is true..

Now statement 2 is tricky a bit..

For which we have to know about conflict miss which occurs more for direct mapped cache and hence which is reduced by increasing the associativity of the cache..Hence in a fully associative cache , number of conflict miss = 0..

Now conflict miss arises due to the fact that two main memory blocks map to the same cache line(in case of direct mapped cache) and same set(in case of set associative cache)..Hence for conflict miss to happen in same cache line , the line offset field should be same ..But in the given statement they are saying about same tag field value.

Regarding statement 3 , there we have the phrase "anti dependency" which is referred to WAR hazards..And register renaming is capable to eliminate that..

Hence statement 2 is false..Hence out of the given statements only 3 is true..

Comments

Thanks habib.Second point is indeed a tricky.  By the term MORE MISSES ,  it means misses apart from Compulsary misses,right? And since a block number is indetified by TAG+Line OFFset and if tag is same ,then Line offset can not be same. Now in this we can have two cases:-

1. Line offset is same. Mens both line and tag offset is same.SO one time miss and all other hit.

2. Line offset is different.It means a compulsary miss. 

In both cases there are not MORE MISSES.

Also, can you share some reference on the 1st point.That all WAW and WAR can be eliminated by register renaming.?The word "eliminated totaly "   gives me doubt

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What I mean by second statement is as we have same tag offset..But it may be possible that we will have different line offset which wont lead to conflict miss which is characteristic of direct mapped cache..

As far WAW and WAR hazards are concerned , u can go through this :

https://en.wikipedia.org/wiki/Register_renaming

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Actually question does not mention conflict missises directly. So,by the word  "more misses"   we are concluding it is conflict misses right?

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@rahul

This is seriously confusing does register renaming eliminate all WAR and WAW hazards or not ?

Because see this :

https://cs.stackexchange.com/questions/30108/does-register-renaming-remove-all-kinds-of-war-hazard

From a computer architecture point of view, an additional problem for write-after-read hazards is dealing with load and store operations to main memory. Register renaming won't help with this problem

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i think 1) WAW and WAR dependencies can be eliminated completly....

          2)RAW dependencies can be reduced but can not eliminate completly(in the case of LOAD and STORE instruction)

          3)CONTROL dependecies also can be reduced but not completly eliminated

please correct me if i am wrong.......

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but war and waw are also hazards and hazards cannot be completely removed by any method, they can be minimised by register renaming, if they can be eliminated can you point out the source of your answer ??