in CO and Architecture
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The access time of cache memory is 45 nsec and that of main memory is 750 nsec. It is found that 75% of memory requests are for read and remaining for write. If the hit access for read and write is 0.9 and 1 respectively and write through protocol is used, then the average memory access time is ________. (in nsec)

Doubt: what is read equation,

0.75[0.9(45)+0.1(45+750)], because write through protocol is used in write equation

In answer given 0.75[0.9(45)+0.1(750)]

where i lag the concept,please help
in CO and Architecture
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2 Comments

They didn't explicitly mention in the question about hierarchal access or related sentence like - "whenever there is a miss in cache, a block of memory is transferred from MM to CM"
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This is the only given,we are asked for answer

what i know

by default me take HierArich
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