IES 2018_Digital Logic_Counter

Question

For what minimum value of propagation delay in each filp-flop will a 10 bit ripple counter skip a count, when it is clocked at 10 MHz?

a) 5 ns

b) 10 ns

c) 20 ns

d) 40 ns

Comments

a)5 ns

Answer 1

Propagation delay is not affected even if the counter skips a count (number of flipflops remain same).

$f<=N*T_p$, where $f$ is the frequency, $N$ is the number of flipflops and $T_p$ is propagation delay.

$T_pmin=\frac{f}{N}=\frac{1}{T*N}sec=\frac{1}{10*10^6*10}sec=10 ns$. (Time period, $T=\frac{1}{f}$)

Comments

@Manoja Rajalakshmi A Could you please explain how is fout = fin / mod works in this case ??

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yes, the number of flipflops will remain the same but it will be counting twice in a single cycle. So it means that the Tclk is faster than it should be. Please correct me, where am i going wrong.

Answer 2

here CLK frequency is given = 10MHz

No of flip flops is given = 10

let Tpd be the propagation delay at each flip flop.

Now the clock frequency must be greater than the max delay in the ckt.

hence T(clk) >= No. of flip flop * Tpd               ----- 1

f (clk) max = 1/ T(clk)              --------2

from equation 1 and 2 :

tpd >= 1/(No of flip flop * f(clk))

by putting the values we will get tpd = 10ns.