Test series

Question

Consider a non-pipeline processor has clock rate of 25 MHz and CPI of 6, another processor designed with same clock rate and 8 stage instruction pipeline. If program containing 500 instructions is executed on both processors, then the speedup factor is _______.

Comments

Formulae should be ..m*n/(m+n-1)

But here they used m*tn/(m+n-1)

m= no of stages , n= no of instructions

tn = max delay in any stage (clock cycles)

As time for sequential = tn*m*n

tpipe= (m+n-1)*tn

..how did u calculated...I'm confused here..

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Don't use direct formula.

Here Time of NP processor = CPI * Instr * Clock time

= 6 * 500 * 1/25 MHZ

Now time for Pipelined proc = 1*8 + 499 = 507 cycles * clock time = 507 * 1/25MHz

Speedup = $\frac{T_{NP}}{T_P} = \frac{6*500*\frac{1}{25Mhz}}{507*\frac{1}{25Mhz}} = \frac{3000}{507} = 5.917$

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Thanks...I think here delay for each stage is not given thus...we can not. Go with the formulae , speedup here is the ratio of number of clock cycles needed indeed ...as factor of frequency gets cancelled....

Correct me if wrong ..!

Answer 1

$\Rightarrow $ Clock Rate = $25$ MHZ

$\Rightarrow \ 1$ cycle time $= \ 0.04$ usec.

$\Rightarrow $ Cycle Per instruction = $6 \Rightarrow 6 \times 0.04=0.24$ usec [$1$ instruction execution time]

For $500$ instruction Execution time :

$\Rightarrow $ Non Pipeline processor = $500 \times 0.24 = 120$ usec

$\Rightarrow $ Pipelined processor = $8 \times 0.04\times 1 +0.04\  \times 499 = 20.28 $ usec

SpeedUp achieved $=\Large \frac{120}{20.28}$ $=\color{Red}{5.917}$

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