Overlapping between Write Back and Decode stage in RISC pipeline.

Question

Somewhere I read that WB and ID stage can overlap, for exaple:- https://gateoverflow.in/753/gate2001-12

and somewhere it is not overlapped. Is it possible to overlap both the stage into a single cycle?

Comments

I think Here they have mentioned WB will be in 1st phase of a cycle. and Read will be in second phase. Hence as soon as half phase of WB is done result is available to ID. for the remaining phase. That's why they overelapped in this question.