Sums on Adder

Question

$1)$3-bit ripple adder, which adds two 3-bit numbers, is designed using AND, OR, NOT, NAND, NOR gates only. Assuming that all the inputs are available in both complemented and uncomplemented forms and the delay of each gate is one time unit, what is the overall propagation delay of the adder

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$2)$3-bit carry look ahead adder, which adds two 3-bit numbers, is designed using AND, OR, NOT, NAND, NOR gates only. Assuming that all the inputs are available in both complemented and uncomplemented forms and the delay of each gate is one time unit, what is the overall propagation delay of the adder?

Comments

(1) 5 time unit using half adder at LSB and 6 time unit using full adder at LSB

(2) 6 time unit.

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@Prateek Raghuvanshi

did you assume n-i/p gates instead of 2-i/p gates

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@Prateek

how?

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@srestha,mam

what  is the fan-in of the gates?

is it 2 ? or n-i/p gates ?

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(1)

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@Prateek Raghuvanshi

i agree, A⊕B⊕C is 2-level ckt

===> All AND gates solved in 1^st T_pd but all OR gates can not solved in 2^nd T_pd. due to it is only 2-i/p OR gate

if it is n-i/p OR gate, then it can be solved in 2^nd T_pd.

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@Shaik

yes for half adder Fan-in 2 and for full adder it will be 3

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@srestha

mam, we doesn't have Half Adders or Full adders in our circuit

we have to implement them also using OR,NOT,AND,NAND,NOR gates

i am asking what is the fan-in of OR gate ( due to answer to 1^st question depend upon it only )

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@ Shaik Masthan yeah you are right ,for OR gate FAN-IN will be n

also in carry look ahead adder , for AND and OR gate  FAN-IN will be n .

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@Prateek Raghuvanshi

brother, i have a doubt.... suppose in the question they didn't mention it ( in this question also ) ...

actually we assume normally it is 2-i/p gates.....if this question ask in some competitive exam then what to do?

which one we have to take 2-i/p or n-i/p ?

any standard resource?

otherwise it's questioner responsibility, to mention if it is n-i/p gates?

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 @ Shaik Masthan brother, they should have to given but if it is not given then we have to assume n-i/p gate because propagation delay will be less that is we want in comparison to 2 i/p gate.

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@Shaik @Prateek

I have answered

Check if any mistake

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@Shaik

yes Full or half adder is not there, but we can make XOR gate with 4 NAND gates

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@Prateek

u wrote directly formula

but is that formula is for XOR gate or for NAND gate?

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mam, why to go Ex-OR implementation by 4 NAND gates?

we can make direct AND-OR realization to reduce the delay

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how? give details

u checked ans?

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let assume OR gate fan-in is doesn't restricted...

Ex-OR = A' . B + A . B'

it is 2-level ===> 2 delays sufficient

Ex-OR = A⊕B⊕C

it is 2-level ===> 2 delays sufficient

but if you go by NAND gate it requires morethan 2 delays

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hmm

what is ur ans?

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same as Prateek

1) 2n-1 ===> LSB is Half Adder

   2n ===> LSB is Full Adder

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with just a formula, how u telling answer is correct?

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mam, that formula directly not get anywhere, that is derived

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then in full adder case

how 2 tpd possible?

according to ur calculation in Sum bit only and for 1 XOR gate 2tpd

then in sum calculation , we need min 2 XOR gate - so 4 tpd

ryt?

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i didn't get you mam

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See. FA2 in that pic

it taken only 2pdfor sum

but according to ur convension there should be 4 tpd

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@Prateek @Shaik

I got 5 time unit for ripple carry adder

and 4 time unit for CLA

Correct now?

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@srestha

mam, give some time to check about CLA, after that i will comment 

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@Prateek Raghuvanshi @srestha In the image above, $C=C_{in}(a⊕b) + ab$ will require 3 levels not 2 as Prateek sir has mentioned!! Wouldn't that make your formula 2n-1 wrong?

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If nothing is mentioned take fan-in for a logic gate = no. of inputs and never use half adder for the 1st stage of full adder computation unless they explicitly mention it because we try to generalize things we don't design the circuit for a particular problem.

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@Shaik Masthan @Prateek Raghuvanshi

for ripple carry adder, can it not possible answer to be $4$?? Say 1st one full adder and 2nd and 3rd half adder??

Ref: https://gateoverflow.in/8250/gate2015-2-48

Answer 1

1) In Ripple Carry Adder, only carry is propagated. So, 3 Full Adder is sufficient to add two 3-bit numbers.

Now,  among these Gates EXOR has maximum propagation delay.

And 1 EXOR can be made of 2 time unit in AND-OR gates. 

If LSB is Half adder,

So, propagation delay will be 2n-1=5 time unit

(Here Carry is propagating with sum)

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2) I tried to put Carry Look Ahead  adder in a diagram.

Here All adder are parallel and carry is propagated

Acc to wiki

• calculation of  $P_{i}$and  $G_{i}$ is done at time 1,
• calculation of $C_{i}$ is done at time 3,
• calculation of the $PG$is done at time 2,
• calculation of the $GG$is done at time 3, 

https://en.wikipedia.org/wiki/Carry-lookahead_adder

Here for 3-bit addition $GG$ will be  2 time  unit and $PG$ will be 2 time unit and $C_{0}$ will be 1 time unit

So, $C_{3}=G_{2}+G_{1}.P_{2}+G_{0}.P_{1}.P_{2}+C_{0}.P_{0}.P_{1}.P_{2}$

here $2+2\times 1=4$ time unit

Ans-4

(In Carry Look Ahead Adder  carry and sum propagating differently . In Ripple Carry and in CLA both case we concentrate only on Carry, not on Sum , as carry propagated upto last both the case )

http://faculty.kfupm.edu.sa/COE/abouh/Lesson3_2.pdf

http://faculty.kfupm.edu.sa/COE/abouh/Lesson3_3.pdf

Comments

@ srestha mam,

there are three level in CLA adder . At 1st level  all $P_i$ and $G_i$ are calculating using x-or and AND gate  since x-or gate is not available so we have to implement x-or gate using basic gate so we can implement x-or gate using two level then only 2 time unit required  on first level .  In 2nd level  we know there is two level circuit in block using AND ,OR gate so here also two time unit is required and at third level we can see there are also X-OR gate so again 2 time unit required , so total 6 time unit required .2 time unit extra are there because X-OR gate is not available direct.

Answer 2

For ripple carry adder answer will be 8 time unit and for carry look ahead adder the answer will be 6 time unit.

In ripple carry adder(n bit adder):- Assuming fan-in atmost 2 and LSB's are computed using full adder.

Tpropagation =(n-1)* T.carry generation time by one full adder+ max(T.carry, T.sum)

   = 2*2  (2 because C=AB+BC+AC can be implemented in 2 levels of AND, OR gate) + max(4, 2)

T.sum=4 because A⊕B⊕C can be implemented using 4 levels of AND, OR gate only if variables are given in both complemented and uncomplemented form.

Tpropagation for ripple carry adder = 8

In carry look ahead adder(n bit adder):-

Carry look ahead adder works in three phases

The first level will take 2 time unit to generate all Pi, Gi terms using AND-OR gate in 2 levels only if variables are given in both complemented and uncomplemented form. similarly 2nd level will also take further 2 time unit for generating the all carry terms and after that to produce the sum terms it will take further 2 time unit. so total propagation delay is 6 time unit.

for more-https://www.gatevidyalay.com/delay-in-ripple-carry-adder/

Comments

Kindly point out my mistake & correct it accordingly. So that I can understand better where I should focus on.

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you r not wrong, but still  I was finding, why two answers giving different result. Concept same na??

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Yeah! We both agree on the same concept, but the problem arises when question doesn't mention fan-in for gates and whether to take half adder or full adder for the LSB computation. But till now GATE questions have been given with proper information about these both, so no point in arguement for non-standard question. I took full adder for LSB computation because of the generalization purpose, so that we could use the same circuit for other computation also(This thing I infered from NPTEL lecture) and by solving more and more questions on "Adder" I am convinced that by default take fan-in= n whenever necessary.