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Recent questions tagged full-adder

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GATE ECE digital logic
A 16-bit ripple carry adder is realized using 16 identical full adders (FA) as shown in the figure. The carry-propagation delay of each FA is 12 ns and the sum propagation delay of each FA is 15 ns. The worst case delay (in ns) of this 16-bit adder will be __________

aditi19 asked in Digital Logic Dec 11, 2018

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Na462 asked in Digital Logic Nov 15, 2018

by Na462

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Full Adder
The Cout function of a 3-bit adder is as follows: AB + Cin (A ⊕ B) ----- i It, being a majority function, can also be written as: AB+BCin+CinA which is equivalent to AB + Cin (A+B) ------- ii So, if we consider eqn i and ii, doesn't it show that (A ⊕ B) = (A+B). What am I missing here?

superak96 asked in Digital Logic Oct 18, 2018

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MCQ-made_eassay
How many full adder are needed to construct m-bit parallel adder ? A. m/2 B. m C. m-1 D. m+1

rishu_darkshadow asked in Digital Logic Dec 14, 2017

by rishu_darkshadow

2.8k views

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5

UGC NET CSE | Junet 2015 | Part 2 | Question: 7
Consider a full-adder with the following input values : $x=1, y=0$ and $C_i$(carry input)$=0$ $x=0, y=1$ and $C_i =1$ Compute the value of S(sum) and $C_o$ (carry output) for the above input values : $S=1, C_o=0$ and $S=0, C_o=1$ $S=0, C_o=0$ and $S=1, C_o=1$ $S=1, C_o=1$ and $S=0, C_o=0$ $S=0, C_o=1$ and $S=1, C_o=0$

go_editor asked in Digital Logic Jul 30, 2016

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Recent questions tagged full-adder