in Digital Logic
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Please explain it i am not understanding the working of it .

in Digital Logic
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I am getting option A !! let me know if its correct or not! if its correct ill explain.
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Initially, (Q1 Q0)=(0,0) so, the decoder should output (0,0,0,1) for (y3, y2, y1, y0) respectively. But because of inverters at the output of the decoder, (y3,y2,y1,y0) are set to (1,1,1,0). Input to preset pin in this case is y3' = 1'=0 and Input to clear pin is (1.1)'=0.
As, both preset=clear=0, FF behaves normally. Since J=K=0, FF is set to Qprevious which is 0. Hence (Q=0, Q'=1). And because Q'=1  "up/down counter"  behaves as "up counter" and outputs (0,1) i.e counter increments the previous value (0,0) in the next clock cycle.So at next clock cycle counter outputs(0,1).

This repeats for the next two cycles giving output (1,0) and (1,1).

Now, when (Q1, Q2)=(1,1) , (y3,y2,y1,y0) are set to (0,1,1,1). Because y3=0, preset becomes 0'=1 and it 'sets' value of JK FF to 1.
hence QA=1 and now "up/down" counter start behaving as a "down counter" so it will output one value lesser than previous that is (1,0).

so sequence we got is  00-01-10-11-10.
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4 Comments

@utkarsh you are right bro
Actually i was not good with the preset and clear logic just I referred it and now i understood Ur solution:)
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okay :)
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which test series is this?? few questions are really good.
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