Login
Register
@
Dark Mode
Profile
Edit my Profile
Messages
My favorites
Register
Activity
Q&A
Questions
Unanswered
Tags
Subjects
Users
Ask
Previous Years
Blogs
New Blog
Exams
Dark Mode
adressing modes
rishabhdevsingh1
asked
in
CO and Architecture
Nov 9, 2018
edited
Aug 3, 2022
by
Shubham Sharma 2
1,149
views
0
votes
0
votes
Given 2 machine instructions,
LW R4 #400
LW R1, 0,(R4)
IN second instruction what will be loaded in R1,is it the operand at memory location 400?or some random memory location operand..I want to clarify whether the value stored in register is same as adress that register points.
co-and-architecture
machine-instruction
addressing-modes
registers
numerical-answers
rishabhdevsingh1
asked
in
CO and Architecture
Nov 9, 2018
edited
Aug 3, 2022
by
Shubham Sharma 2
by
rishabhdevsingh1
1.1k
views
answer
comment
Follow
share this
share
1 comment
by
rishabhdevsingh1
commented
Nov 9, 2018
reply
Follow
share this
please answer. it would be a great help.
0
0
Please
log in
or
register
to add a comment.
Please
log in
or
register
to answer this question.
1
Answer
1
vote
1
vote
It will not be some random value - the second instruction is an example of indexed addressing mode.
It means that the value of R4 with an offset of 0 will be loaded.
However, it varies from ISA to ISA - what the actual syntax of the instruction is.
goxul
answered
Nov 9, 2018
by
goxul
comment
Follow
share this
4 Comments
Show 4 previous comments
by
rishabhdevsingh1
commented
Nov 9, 2018
edited
Nov 9, 2018
by
rishabhdevsingh1
reply
Follow
share this
ok. the complete question is something like..
LW R4#400
L1: LW R1, 0,(R4)
LW R2, 400(R4)
ADDI R3, R1, R2
SW R3, 0(R4)
SUB R4, R4, #4
BNEZ R4, L1
HOW MANY TIMES WILL THE LOOP RUN
0
0
by
goxul
commented
Nov 9, 2018
reply
Follow
share this
I guess 100?
Inside the loop, we store the value stored at R4 and R4+400 in R1 and R2 respectively.
The third line doesn't make a lot of sense though - we are storing the contents of R3 into R4, but there's no mention of what R3 actually contains.
As I said, what is the instruction set architecture given? What do the instructions mean?
Can you post the entire question as a new question?
0
0
by
rishabhdevsingh1
commented
Nov 9, 2018
reply
Follow
share this
what about 4th instruction? architecture is not given. I think, by default RISC architecture will be considered.
0
0
Please
log in
or
register
to add a comment.
← Previous
Next →
← Previous in category
Next in category →
Related questions
0
votes
0
votes
0
answers
1
rishabhdevsingh1
asked
in
CO and Architecture
Nov 10, 2018
616
views
adressing modes
For Given machine instructions LW R4 #400 L1:LW R1, 0,(R4) LW R2 400(R4) ADDI R3, R1, R2 SW R3, 0(R4) SUB R4, R4, #4 BNZ R4, L1 on a 5 stage pipeline processor, 1 clock cycle per stage. how mAny clock cycles willtake execution of this segment on the regular architecture?
rishabhdevsingh1
asked
in
CO and Architecture
Nov 10, 2018
by
rishabhdevsingh1
616
views
co-and-architecture
machine-instruction
registers
pipelining
addressing-modes
numerical-answers
4
votes
4
votes
2
answers
2
Na462
asked
in
CO and Architecture
Jul 31, 2018
2,168
views
Instruction Addressing
A computer has 170 different operations. Word size is 4 bytes one word instructions requires two address fields. One address for register and one address for memory. If there are 37 registers then the memory size is ______________(in KB). Ans. 256KB
Na462
asked
in
CO and Architecture
Jul 31, 2018
by
Na462
2.2k
views
co-and-architecture
addressing-modes
machine-instruction
12
votes
12
votes
3
answers
3
Tehreem
asked
in
CO and Architecture
Sep 9, 2015
11,750
views
Max number of one address instruction, when two address instruction is given is?
A computer uses expanding opcode. It has 16 bit instructions 6 bit addresses, it supports one address, two address instructions only. If there are n two address instructions, the maximum number of one address instructions are?
Tehreem
asked
in
CO and Architecture
Sep 9, 2015
by
Tehreem
11.8k
views
co-and-architecture
addressing-modes
machine-instruction
instruction-format
0
votes
0
votes
2
answers
4
anjali007
asked
in
CO and Architecture
Dec 4, 2018
484
views
TestBook- Addressing Modes
A register to register machine supports 2–address, 1-address and zero–address instructions. Instruction register size is 24 bits and register set size is 480. If there are 48 2–address instructions and 2048 zero – address instructions then what is the maximum possible number of 1 – address instruction?
anjali007
asked
in
CO and Architecture
Dec 4, 2018
by
anjali007
484
views
co-and-architecture
addressing-modes
testbook-test-series
numerical-answers
Subscribe to GATE CSE 2024 Test Series
Subscribe to GO Classes for GATE CSE 2024
Quick search syntax
tags
tag:apple
author
user:martin
title
title:apple
content
content:apple
exclude
-tag:apple
force match
+apple
views
views:100
score
score:10
answers
answers:2
is accepted
isaccepted:true
is closed
isclosed:true
Recent Posts
Post GATE 2024 Guidance [Counseling tips and resources]
GATE CSE 2024 Result Responses
[Project Contest] Pytorch backend support for MLCommons Cpp Inference implementation
Participating in MLCommons Inference v4.0 submission (deadline is February 23 12pm IST)
IIITH PGEE 2024 Test Series by GO Classes
Subjects
All categories
General Aptitude
(3.5k)
Engineering Mathematics
(10.4k)
Digital Logic
(3.6k)
Programming and DS
(6.2k)
Algorithms
(4.8k)
Theory of Computation
(6.9k)
Compiler Design
(2.5k)
Operating System
(5.2k)
Databases
(4.8k)
CO and Architecture
(4.0k)
Computer Networks
(4.9k)
Artificial Intelligence
(79)
Machine Learning
(48)
Data Mining and Warehousing
(25)
Non GATE
(1.4k)
Others
(2.7k)
Admissions
(684)
Exam Queries
(1.6k)
Tier 1 Placement Questions
(17)
Job Queries
(80)
Projects
(11)
Unknown Category
(870)
64.3k
questions
77.9k
answers
244k
comments
80.0k
users
Recent Blog Comments
category ?
Hi @Arjun sir, I have obtained a score of 591 in ...
download here
Can you please tell about IIT-H mtech CSE self...
Please add your admission queries here:...
Twitter
WhatsApp
Facebook
Reddit
LinkedIn
Email
Link Copied!
Copy