adressing modes

Question

For Given machine instructions

LW R4 #400

L1:LW R1, 0,(R4)

LW R2 400(R4)

ADDI R3, R1, R2

SW R3, 0(R4)

SUB R4, R4, #4

BNZ R4, L1
on a 5 stage pipeline processor, 1 clock cycle per stage. how mAny clock cycles willtake execution of this segment on the regular architecture?

Comments

lw ????

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To consider,

LW :LOAD WORD

SW: STORE RESULT

BNEZ R4, L1 , LOOP IF (R4) !=0

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OKK  I MAINLY READ ONLY LD  AND ST FOR EVERYTHING, NEVER SEE THIS CONVENTION.

still i think question is incomplete . we dont about how many cycles for load etc , sub operation.

if we dont know cycles how can we go for loop etc ?????

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updated the question. now can you solve this?