Madeeasy-Test-series

Question

consider a RISC processor with an ideal CPI, where 25% of total instructions are Load and Store instructions. The time to access the main memory is 100 clock cycles and accessing of the cache memory required 2 clock cycles. if the cache miss rate is 2%, then the effective CPI for the system with the cache is __.{up to 2 decimal}.

Comments

There is nothing given like that  ,then we can't assume anything for getting answer.

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I think we can do it this way:

Memory Stall Cycles = IC * (MemoryAccess/Instruction) * Miss Rate * Miss Time = 1.25*0.02*100
Memory Hit Cycles = IC * (Memory Access / Instruction) * Hit Rate * Hit Time = 1.25*0.98*2

Memory Access / Instruction will be 1.25 (1 + 0.25) since 25 % of the instructions are Load/Store. Here one represents the instruction access and 0.25 represents the data access.

So total number of cycles will be the sum of both, which comes to IC*4.95.

So average CPI will be memory cycles/IC, giving the answer as 4.95.

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There was a somewhat similar question here. Look at how they've calculated MemAcc/Instruction.