Risc Pipelining, CPI (cycles per instruction)

Question

In a pipelined RISC computer where all arithmetic instructions have the same CPI (cycles per instruction), which of the following actions would improve the execution time of a typical program?

I. Increasing the clock cycle rate

II. Disallowing any forwarding in the pipeline

III. Doubling the sizes of the instruction cache and the data cache without changing the clock cycle time

(A) I only (B) II only (C) III only (D) I and II (E) I and III

Answer 1

1. True

2. Forwarding reduces pipeline hazard so cant be correct, False.

3. True, bcz larger cache size will hold more data and possibly lower cache miss rate.

Comments

For 3 it is the other way around. Increasing cache size can in no way reduce performance (assuming hardware is scaled properly), but increasing the cache block might reduce performance as it might increase the transfer time for each block though it can reduce the compulsory misses.

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@Arjun sir- then the answer would be TFT ?

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yes.. it should be E option.

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How does increasing clock cycle rate help in improving???? Does increasing clock cylce rate means reducing clock cycle time??