$\text{1) Master-Slave FF is designed to avoid race around condition - TRUE}$
In $SR$ flip-flop we have output ends $Q$ and $\overline{Q}$ respectively, when both the inputs are 1 then output is indeterminate. In order to remove this behavior we connect output $Q$ to $R$ and $\overline{Q}$ to S. This creates toggling and the toggling is so fast that we can't even remove it by giving clock pulse of size less than time required to toggle. This toggle is nothing but the race condition. So to avoid this problem we use $\text{Master-Slave FF}$ where the output of $\text{Master FF}$ becomes available at the $\text{SLAVE}$ end after 1 clock cycle.
$\text{2) Master-Slave FF is used to store 2 bit information - FALSE}$
We are storing only 1 bit information, the only difference here is that 1 bit information appears at the output end with a delay of 1 clock cycle.
$\textbf{PS: Edit}$
When the clock pulse is active Master FF output is available but does not appear at output end and during the same cycle Slave FF has output which was produced by Master FF in previous cycle. Once again when clock cycle becomes down, then slave becomes active and Master FF's output will appear the Slave FF end. Hence it appear that it is storing 2 bit information, but actually it is storing 1 bit of information.
