Login
Register
@
Dark Mode
Profile
Edit my Profile
Messages
My favorites
Register
Activity
Q&A
Questions
Unanswered
Tags
Subjects
Users
Ask
Previous Years
Blogs
New Blog
Exams
Dark Mode
NPTEL Assignment Question
rsansiya111
asked
in
CO and Architecture
Dec 8, 2021
199
views
0
votes
0
votes
nptel-quiz
rsansiya111
asked
in
CO and Architecture
Dec 8, 2021
by
rsansiya111
199
views
answer
comment
Follow
share this
share
1 comment
by
raja11sep
commented
Dec 8, 2021
reply
Follow
share this
Answer: B
0
0
Please
log in
or
register
to add a comment.
Please
log in
or
register
to answer this question.
0
Answers
← Previous
Next →
← Previous in category
Next in category →
Related questions
1
vote
1
vote
0
answers
1
lalitver10
asked
in
CO and Architecture
Jan 12, 2023
234
views
NPTEL Assignment
Question : i. CISC architecture a. Symmetric registers ii. RISC architecture b. Multiple memory references iii. Misalignment c. Condition code register iv. Static data d. Single memory reference Options: i-a,ii-c,iii-b,iv-d i-c,ii-a,iii-b,iv-d i-c,ii-a,iii-b,iv-b i-c,ii-a,iii-d,iv-b
lalitver10
asked
in
CO and Architecture
Jan 12, 2023
by
lalitver10
234
views
nptel-quiz
co-and-architecture
0
votes
0
votes
0
answers
2
rsansiya111
asked
in
CO and Architecture
Dec 8, 2021
368
views
NPTEL Assignment Question
Consider the following code : Load R1,M Load R2,N CMP R1,R2 JGE END Store [300],R2 END: Store [300],R1 Assume that M=30 and N=25. The above sequence of instructions is to be executed on a pipelined processor with IF , ... instructions. The branch outcome is known after EX stage. Determine the number of clock cycles required for completion of execution of all instructions.
rsansiya111
asked
in
CO and Architecture
Dec 8, 2021
by
rsansiya111
368
views
co-and-architecture
pipelining
operand-forwarding
nptel-quiz
branch-conditional-instructions
3
votes
3
votes
1
answer
3
LRU
asked
in
CO and Architecture
Dec 4, 2021
1,141
views
NPTEL Assignment
Consider a direct-mapped cache with 64 blocks and a block size of 16 bytes. Byte address 1200 will map to block number ………… of the cache.
LRU
asked
in
CO and Architecture
Dec 4, 2021
by
LRU
1.1k
views
nptel-quiz
co-and-architecture
cache-memory
2
votes
2
votes
1
answer
4
LRU
asked
in
CO and Architecture
Dec 4, 2021
573
views
NPTEL Assignment
Consider a two-level memory hierarchy with separate instruction and data caches in level 1, and main memory in level 2. The clock cycle time in 1 ns. The miss penalty is 20 clock cycles for both read and write. 2% of the instructions are not found ... access time (including hit detection) is 1 clock cycle. The average access time of the memory hierarchy will be . nanoseconds
LRU
asked
in
CO and Architecture
Dec 4, 2021
by
LRU
573
views
nptel-quiz
co-and-architecture
effective-memory-access
Subscribe to GATE CSE 2024 Test Series
Subscribe to GO Classes for GATE CSE 2024
Quick search syntax
tags
tag:apple
author
user:martin
title
title:apple
content
content:apple
exclude
-tag:apple
force match
+apple
views
views:100
score
score:10
answers
answers:2
is accepted
isaccepted:true
is closed
isclosed:true
Recent Posts
Post GATE 2024 Guidance [Counseling tips and resources]
GATE CSE 2024 Result Responses
[Project Contest] Pytorch backend support for MLCommons Cpp Inference implementation
Participating in MLCommons Inference v4.0 submission (deadline is February 23 12pm IST)
IIITH PGEE 2024 Test Series by GO Classes
Subjects
All categories
General Aptitude
(3.5k)
Engineering Mathematics
(10.4k)
Digital Logic
(3.6k)
Programming and DS
(6.2k)
Algorithms
(4.8k)
Theory of Computation
(6.9k)
Compiler Design
(2.5k)
Operating System
(5.2k)
Databases
(4.8k)
CO and Architecture
(4.0k)
Computer Networks
(4.9k)
Artificial Intelligence
(79)
Machine Learning
(48)
Data Mining and Warehousing
(25)
Non GATE
(1.4k)
Others
(2.7k)
Admissions
(684)
Exam Queries
(1.6k)
Tier 1 Placement Questions
(17)
Job Queries
(80)
Projects
(11)
Unknown Category
(870)
64.3k
questions
77.9k
answers
244k
comments
80.0k
users
Recent Blog Comments
category ?
Hi @Arjun sir, I have obtained a score of 591 in ...
download here
Can you please tell about IIT-H mtech CSE self...
Please add your admission queries here:...
Twitter
WhatsApp
Facebook
Reddit
LinkedIn
Email
Link Copied!
Copy
