Login
Register
@
Dark Mode
Profile
Edit my Profile
Messages
My favorites
Register
Activity
Q&A
Questions
Unanswered
Tags
Subjects
Users
Ask
Previous Years
Blogs
New Blog
Exams
Dark Mode
Conflict Misses
Sumit1311
asked
in
CO and Architecture
Jan 21, 2016
retagged
Nov 13, 2017
by
Arjun
607
views
1
vote
1
vote
Will conflict misses increase if k-way set associative cache is used and we increase the cache capacity?
co-and-architecture
cache-memory
misses
Sumit1311
asked
in
CO and Architecture
Jan 21, 2016
retagged
Nov 13, 2017
by
Arjun
by
Sumit1311
607
views
answer
comment
Follow
share this
share
3 Comments
by
Sushant Gokhale
commented
Jan 22, 2016
reply
Follow
share this
Whats the previous architecture?
0
0
by
Sumit1311
commented
Jan 22, 2016
reply
Follow
share this
I didn't get you. Can you explain a bit?
0
0
by
Sushant Gokhale
commented
Feb 25, 2016
reply
Follow
share this
I am sorry. I asked something baseless. Sticking to the definition of a conflict miss, I think the conflict misses should decrease because now, there will be less no of RAM blocks mapped to the same set.
1
1
Please
log in
or
register
to add a comment.
Please
log in
or
register
to answer this question.
1
Answer
4
votes
4
votes
If we increase cache size in k-way set associative cache then number of set will increase and number of block mapped to the same set will decrease and hence conflict miss will decrease
vijaycs
answered
May 13, 2016
by
vijaycs
comment
Follow
share this
0 Comments
Please
log in
or
register
to add a comment.
← Previous
Next →
← Previous in category
Next in category →
Related questions
0
votes
0
votes
0
answers
1
bts1jimin
asked
in
CO and Architecture
Jan 17, 2019
454
views
find conflict misses
here it is given byte addressable. So these locations refer to words or byte location. What are set, block fields here : number of words or number of bytes for these location.
bts1jimin
asked
in
CO and Architecture
Jan 17, 2019
by
bts1jimin
454
views
co-and-architecture
misses
cache-memory
1
vote
1
vote
0
answers
2
Na462
asked
in
CO and Architecture
Jan 21, 2019
922
views
Ace Test Series: CO & Architecture - Cache Misses Type
Na462
asked
in
CO and Architecture
Jan 21, 2019
by
Na462
922
views
cache-memory
co-and-architecture
misses
ace-test-series
0
votes
0
votes
0
answers
3
Na462
asked
in
CO and Architecture
Jul 29, 2018
527
views
Misses
Consider the system have L1 data cache with 50 percent of hit rate and take 2 cycles when hit in L1 cache, L2 cache with 70% of hit rate and take 15 cycles when hit in L2 cache and main memory with 100% of hit rate and 200 cycles when hit in main memory to access a block. If main memory speed is improved 15%, then the improvement in L1 miss time is ________. (upto 2 decimal place)
Na462
asked
in
CO and Architecture
Jul 29, 2018
by
Na462
527
views
co-and-architecture
misses
cache-memory
0
votes
0
votes
1
answer
4
Na462
asked
in
CO and Architecture
Jul 29, 2018
881
views
No. of Misses
Assume that we have a two dimensional array of 60 × 60. Each element is of 4 bytes and array is stored in row major order. RAM is 2 MB and cache is 8 KB with each block of 16 bytes. In case of direct mapped cache, the number of cache misses are _______ (Assume that cache is empty initially). Ans. 1288
Na462
asked
in
CO and Architecture
Jul 29, 2018
by
Na462
881
views
co-and-architecture
misses
cache-memory
direct-mapping
Subscribe to GATE CSE 2024 Test Series
Subscribe to GO Classes for GATE CSE 2024
Quick search syntax
tags
tag:apple
author
user:martin
title
title:apple
content
content:apple
exclude
-tag:apple
force match
+apple
views
views:100
score
score:10
answers
answers:2
is accepted
isaccepted:true
is closed
isclosed:true
Recent Posts
Post GATE 2024 Guidance [Counseling tips and resources]
GATE CSE 2024 Result Responses
[Project Contest] Pytorch backend support for MLCommons Cpp Inference implementation
Participating in MLCommons Inference v4.0 submission (deadline is February 23 12pm IST)
IIITH PGEE 2024 Test Series by GO Classes
Subjects
All categories
General Aptitude
(3.5k)
Engineering Mathematics
(10.4k)
Digital Logic
(3.6k)
Programming and DS
(6.2k)
Algorithms
(4.8k)
Theory of Computation
(6.9k)
Compiler Design
(2.5k)
Operating System
(5.2k)
Databases
(4.8k)
CO and Architecture
(4.0k)
Computer Networks
(4.9k)
Artificial Intelligence
(79)
Machine Learning
(48)
Data Mining and Warehousing
(25)
Non GATE
(1.4k)
Others
(2.7k)
Admissions
(684)
Exam Queries
(1.6k)
Tier 1 Placement Questions
(17)
Job Queries
(80)
Projects
(11)
Unknown Category
(870)
64.3k
questions
77.9k
answers
244k
comments
80.0k
users
Recent Blog Comments
category ?
Hi @Arjun sir, I have obtained a score of 591 in ...
download here
Can you please tell about IIT-H mtech CSE self...
Please add your admission queries here:...
Twitter
WhatsApp
Facebook
Reddit
LinkedIn
Email
Link Copied!
Copy