This question gets a lot more easier if you are aware of the cases for which 2’s complement addition / subtraction gives overflow ( Nicely answered by @gatecse) . This circuit is an 2’s complement adder-subtractor circuit which performs addition if S=0 and subtraction if S=1
But if not , we can approach this simply based on basic properties of 2’s complement signed representation
For 4-bit 2’s complement notation , range : [-8,7] ( -2(N-1), 2(N-1)-1)
So if we get a result out of this range , we get an overflow
For Options A and B , S=0 , so B doesnt change after xor operation
Option A) A = 7 , B = -8 (2’s complement form)
now A+B+S = 7-8+1=0 ( within the range )
So there is no overflow
Option B) A = -4 , B = -6
now A+B+S = -4-6+0 = -10 ( out of range )
So there will be overflow
Option C) A = 7 , B = 6
(Make sure to complement B because S=1 → exor causes complementation)
now A+B+S = 7+6+1 = 14 ( out of range )
So there will be overflow
Option D) A = 5 , B = 1
now A+B+S = 5+1+1 = 7 ( within range )
So there is no overflow
Therefore , ANS: B,C