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5 votes
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Consider the following $4$-bit adder circuit.


Note, $\text{C}_0$ is carry in and $\text{C}_4$ is carry out for the $4$-bit adder. The given circuit operates on $\text{2's}$ complement numbers.

In the given circuit, overflow occurs for:

  1. $\text{A}_3 \text{A} _2 \text{A}_1 \text{A}_0=0111, \text{B}_3 \text{B}_2 \text{B}_1 \text{B}_0=1000$ and $\text{S}=0$
  2. $\text{A}_3 \text{A}_2 \text{A}_1 A 0=1100, \text{B}_3 \text{B}_2 \text{B}_1 \text{B}_0=1010$ and $\text{S}=0$
  3. $\text{A}_3 \text{A}_2 \text{A}_1 A 0=0111, \text{B}_3 \text{B}_2 \text{B}_1 \text{B}_0=1001$ and $\text{S}=1$
  4. $\text{A}_3 \text{A}_2 \text{A}_1 A 0=0101, \text{B}_3 \text{B}_2 \text{B}_1 \text{B}_0=1110$ and $\text{S}=1$
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2 Answers

7 votes
7 votes

This adder and subtractor unit operates on $\text{2's}$ complement numbers and the $\mathrm{S}$ input signal determines whether an addition or subtraction will occur.

  • In $\text{2's}$ complement addition, overflow occurs if both operands are positive but the result is negative, or if both operands are negative and the result is positive.
     
  • In $\text{2's}$ complement subtraction, overflow occurs if a positive number is subtracted from a negative number and the result is positive, or if a negative number is subtracted from a positive number and the result is negative.
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4 Comments

Input S signal if 0 does it mean addition or substraction please clarify this
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It means addition
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Anyone can clarify, what 2’s complement here is for ??
I thought like 1st for S=0 it's simple same as B {[xor by 0 same as input]} and then addition with A and carry as 0.
in A didn’t get overflow output as – 
          0111 + 1000 = 1111

same for others and I get overflow condition [that extra carry] in option B only can someone help me with this question?
 

 

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@trail  S=1 means subtractions

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2 votes
2 votes

This question gets a lot more easier if you are aware of the cases for which 2’s complement addition / subtraction gives overflow ( Nicely answered by @gatecse) . This circuit is an 2’s complement adder-subtractor circuit which performs addition if S=0 and subtraction if S=1
But if not , we can approach this simply based on basic properties of 2’s complement signed representation
For 4-bit 2’s complement notation , range : [-8,7] ( -2(N-1), 2(N-1)-1)
So if we get a result out of this range , we get an overflow 
For Options A and B , S=0 , so B doesnt change after xor operation
Option A) A = 7 , B = -8 (2’s complement form)
now A+B+S = 7-8+1=0 ( within the range )
So there is no overflow 
Option B) A = -4 , B = -6 
now A+B+S = -4-6+0 = -10 ( out of range )
So there will be overflow 
Option C) A = 7 , B = 6
(Make sure to complement B because S=1 → exor causes complementation) 
now A+B+S = 7+6+1 = 14 ( out of range )
So there will be overflow 
Option D) A = 5 , B = 1 
now A+B+S = 5+1+1 = 7 ( within range )
So there is no overflow 
Therefore , ANS: B,C

Answer:

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