MADE EASY TEST SERIES 2024 #COA

Question

Consider 16 bit CPU with 4 GB RAM supports 2 Address Instruction with Address 1 uses direct addressing mode Address2 uses indirect addressing mode. Opcode is designed as ADD operation with Address 1 used as Source1 and Destination, Address2 used as Source2. System supports 1 word opcode. CPU cycle time is 2 ns. ALU operation consumes 4 cycles. Memory reference consumes 6 cycles. Time required to complete the instruction is in (ns).

Comments

i think anwer should be  116nsec

5 memory reference for fetch and decode

3 memory reference for operand fetch

4 cycle for ALU and

1 memory reference for write

overall 116 nsec

Answer 1

1. Fetching Address1 (Direct Addressing): This involves updating the program counter (PC) and accessing memory to fetch the value at Address1. Assuming a simple memory access scheme, it takes:

   • 1 cycle for PC update
   • 1 cycle for memory access

2. Fetching Address2 (Indirect Addressing): This involves two steps:

   • Fetch the value at Address1: Similar to step 1, it takes 1 cycle for PC update and 1 cycle for memory access.
   • Dereference the value: Use the fetched value as an address to access memory and fetch the actual operand (Source2). This takes an additional 6 cycles for memory access.

3. ALU Operation: Once both operands are available, the ALU performs the addition operation, taking 4 cycles.

Therefore, the total time required to complete the instruction is:

• Fetch Address1: 1 cycle + 1 cycle = 2 cycles
• Fetch Address2: 1 cycle + 1 cycle + 6 cycles = 8 cycles
• ALU Operation: 4 cycles

Adding these up, we get:

• Total time = 2 cycles + 8 cycles + 4 cycles = 14 cycles

Finally, convert the cycle time to nanoseconds:

• Time in ns = 14 cycles * 2 ns/cycle = 28 ns

Comments

won't Indirect addressing take 2 Memory references?

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Yes I was thinking the same. I think he has given wrong answer.

Answer 2

1. Opcode fetch (1 word opcode):

   • Fetch Opcode from memory (1 cycle): 6 cycles (Memory reference)

2. Operand fetch for Source1 (Direct addressing mode - 1 word):

   • Fetch Operand from memory (1 cycle): 6 cycles (Memory reference)

3. Operand fetch for Source2 (Indirect addressing mode - 1 word):

   • Fetch Address2 from memory (1 cycle): 6 cycles (Memory reference)
   • Fetch Operand from the indirect address (1 cycle): 6 cycles (Memory reference)

4. ALU operation (ADD):

   • Execute ADD operation (4 cycles): 4 cycles (ALU operation)

5. Store result back to the destination:

   • Store result in memory (1 cycle): 6 cycles (Memory reference)

Now, add up the cycles: 6 (Opcode)+6 (Source1)+6 (Address2)+4 (ALU)+6 (Store)=28 cycles6(Opcode)+6(Source1)+6(Address2)+4(ALU)+6(Store)=28cycles

The CPU cycle time is 2 ns, so the total time required to complete the instruction is: 28 cycles×2 ns/cycle=56 ns28cycles×2ns/cycle=56ns

Therefore, the time required to complete the instruction is 56 ns.

Answer 3

Given Instruction is  

ADD

[A1]

[[A2]]

 

Now to fetch the Given Instruction we need 1 memory reference 

For Address 1 we need 1 Memory Reference.

For Address 2 we need 2 Memory references.

Now to store back the result in Destination Address 1 we need 1 memory reference. 

Total no of memory references = 1+1+2+1 = 5 * 6cycle/reference = 30 cycles.

Before storing the result we need to perform the ADD operation 

M[A1] ← M[A1] + M[[A2]]

It takes 4 cycles given in the problem statement. 

Total 34 cylces.

Each cycle take 2ns , So 34*2 = 68ns.