GATE CSE 2005 | Question: 80

Question

Consider the following data path of a $\text{CPU}.$

The $\text{ALU},$ the bus and all the registers in the data path are of identical size. All operations including incrementation of the $\text{PC}$ and the $\text{GPRs}$ are to be carried out in the $\text{ALU}.$ Two clock cycles are needed for memory read operation – the first one for loading address in the $\text{MAR}$ and the next one for loading data from the memory bus into the $\text{MDR}.$

The instruction "call Rn, sub” is a two word instruction. Assuming that $\text{PC}$ is incremented during the fetch cycle of the first word of the instruction, its register transfer interpretation is

$\text{Rn} \leftarrow \text{PC} + 1$;

$\text{PC} \leftarrow \text{M[PC]}$;

The minimum number of CPU clock cycles needed during the execution cycle of this instruction is:

• A. $2$
• B. $3$
• C. $4$
• D. $5$

Comments

@srestha

Does they asked for it?

Even if they didn't ask then how are you planning to do it ?

They asked to show the execute cycle of "call Rn, sub”.

And that maynot even require PC,GPR,S or T(as shown in diagram) , those thing when this subroutine is calling.

Please, can you write down the steps for $"call\ Rn,sub"$ which you think is valid.

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@Kushagra गुप्ता

I think like this.

Though the question is asking for execution cycle, but in this subroutine call instruction, there is nothing to execute. Like add, subtract or branching like operation. 

So, what is need to be perform here, nothing but Fetch cycle.

Steps are

1) First Fetch address of the subroutine. Put MAR value in PC.

2)Increment PC value. As it is a memory read operation, wait for Memory Function Complete Signal(WMFC).

3) Fetch data By MDR and put it in IR.

Let me know, if it is correct.

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someone please provide video lecture link related to this concept

Answer 1

My interpretation:

call Rn - word1
Sub-  word2 (sub routine address)

After fetching word1 PC in incremented. So PC points to word 2. (already completed in fetch cycle)
We need to store the return address that means address of instruction after call. Means, We have to store PC+1 value.
Here we are storing it in Reg Rn.
Next, We need to jump to subroutine. So we are loading subroutine address (M[PC]) into PC.

No of execution cycles=3 (as told in this comments section.)

Answer 2

The answer will be 3.

Explanation :

Execution Cycle = (PC + 1(Compute), which needs 0 clock cycle, already calculated in Fetch cycle) + M[PC] (which needs 2 clock cycles) + WB (which needs 1 clock cycle, register write)

now for WB the operations are :

R_n←Res(PC+1)

PC←M[PC] 

both of these instructions can be done parellely since none of them are dependent.

Answer 3

Pardon for bad handwriting.

Answer 4

Rn←PC+1;

PC←M[PC];

 

T1: $PC_{out}$, $Select_{Y}$,$Rn_{in},ADD,Z_{in}$

T2: WMFC(Wait for Memory Function complete)

T3: $Z_{out}$,$PC_{in}$