GATE CSE 2000 | Question: 2.12

Question

The following arrangement of master-slave flip flops

has the initial state of $P, Q$ as $0, 1$ (respectively). After three clock cycles the output state $P, Q$ is (respectively),

• A. $1, 0$
• B. $1, 1$
• C. $0, 0$
• D. $0, 1$

Comments

Thanks for replying !!

In asynchronous counter the output of 1 FF is given to other FF and I thnkt because of that it's Asynchronous .

Pleaee Correct me if I am wrong.

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Yes, you are right that in asynchronous counter the output of 1FF is given to other FF but the output is given as the  Clock of other FF while in the synchronous we have same clock.

Please Correct me if I am wrong.

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After three clock cycle output states P,Q is 1,0 (no change in answer)

Answer 1

Here, clocks are applied to both flip flops simultaneously. Outputs for $3$ cycles will proceed as follows:

• When $11$ is applied to $JK$ flip flop it toggles the value of $P.$ So, output at  $P$ will be $1.$
• Input to D flip flop will be $0$ (initial value of P).  So, output at $Q$ will be $0.$

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  $JK$ flip flop it toggles the value of $P.$ So, output at  $P$ will be $0.$

• Input to D flip flop will be $1$ (current value of P) . So, output at $Q$ will be $1.$

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• $JK$ flip flop it toggles the value of $P.$ So, output at  $P$ will be $1.$
• Input to D flip flop will be $0$ (initial value of P)  so output at $Q$ will be $0.$

So, answer is A.

Comments

JK-11 and previous state of P is 0, so next state of P will be 1. right?

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but he is given to assume as master slave did it mean i need negation of the clock to the D-flip flop??

plz explain i am confused

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@Arjun Sir,
IF the question were to calculate the output after 3 clock cycles  . Would the answer be 1,1...?
IS my approach correct ?

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PC how do you get p=1 in cyle 2 when j=1,k=1 ,toggle happens it means previously p=1 after toggle p=0 na

u may get 01,10,01,10 ............

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Yeah , u r correct . I did a mistake .

thx :)

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It is given as a master slave FF then why the clock is not inverted for second FF?

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Same Doubt!

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The first FF is a master slave FF while 2nd one is a D FF, so the clock inversion happens within the first FF.

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P$_{N}$ = $\sim$P

Q$_{N}$ = P

P	Q	P$_{N}$	Q$_{N}$
0	1	1	0
1	0	0	1
0	1	1	0

 

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$P_{Next} = JP'+K'P = 1P'+1'P = P'$

$Q_{Next} = D = P$

$P$	$Q$	$P_{Next}$	$Q_{Next}$
0	0	1	0
0	1	1	0
1	0	0	1
1	1	0	1

State Diagram:

So, the correct answer is $(A)$.

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@laxman Patel how did you form the the expression for PNext....please elaborate

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@Doley

In general $:Q_{Next} = J\:\overline{Q} + \overline{K}\:Q$

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In the first clock itself when the clock is high:

As we know that clock time is generally smaller than the delay due to FF, when the output of J-K becomes 1 before the clock goes low, the output of D will change to 1. So at the end of cycle one, the output seems to become 1 1.

Similarly after clock cycle two and three output will become: 0 0 and 1 1 respectively.

@Lakshman Bhaiya kindly correct me.

Answer 2

now when clock is aplied J= 1 and K=1 then (it do complement of P) i.,e output at p = 1 and at same time FF D has input 0 so it change Output Q as ) only [ on D-FF input = output]

SO output will be p= 1 and Q= 0 

[ keep in mind both FF work at same time dont wait for 1st complete then second will start].

Comments

@sittian  hopw you got it now.

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You are not getting this ia synchronous ckt I.e. clock is not present on any FF . Both FF work at together here .. Check clock input properly..

Input to D comes from JK FF not

Answer 3

first find the next state for jk-ff and d-ff  which is p(n+1)=not(p) and q(n+1)=d=p
given in question p=0 and q=1 so next state for p=1 and q=0
so a is ans

Answer 4

-> As there is Master Slave configuration, 1st flipflop will respond to the positive edges and the 2nd flipflop to the negative edges.

-> As the given Flipflops are synchronous,(clock is simultaneously given to both FFs) $Q$ responds according to immediate values of $P$.

-> Thus, after 3 cycles, as shown in the diagram, $P = 1$ and $Q=0$