pipeline

Question

Consider an unpipelined processor. Assume that it has 1-ns clock cycle and that it uses 4 cycles for ALU operations and 5 cycles for branches and 4 cycles for memory operations. Assume that the relative frequencies of these operations are 50 %, 35 % and 15 % respectively. Suppose that due to clock skew and set up, pipelining the processor adds 0.15 ns of overhead to the clock. Ignoring any latency impact, how much speed up in the instruction execution rate will we gain from a pipeline?

Answer 1

Non-pipeline CPI = 4.35

In the pipeline, the clock is = 1.15ns (because of clock skew and set up).

SpeedUP = $\\ \frac{\text{Time to execute one instruction in non pipeline}}{\text{Time to execute one instruction in pipeline}} \\ \\ \frac{4.35}{1.15}\\ \\3.78\\$

Comments

please explain the solution in more detail

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How CPI is 1 here in pipeline execution???

cycles is not same for all instructions.

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did you find how 'Tp' is 1 for pipelined processor?

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I hate these kind of people, acting all genius. Give some explanation at least if you are going to provide answer.

Answer 2

For pipelined processer

Execution time =1+0.15=1.15

For non-pipeline processer

Execution time = 4*50/100+5*35/100+4*15/100=4.35

Speed up= 4.35/1.15=3.78