Classic RISC Pipeline

Question

In which stage of the classic RISC pipeline, operand is fetched. Is it in Instruction Decode or Execute (ALU) stage?

Comments

In the classic RISC (Reduced Instruction Set Computing) pipeline, the operand fetching typically occurs in the Instruction Decode stage. This stage is also known as the "Decode" or "ID" stage.

During the Instruction Decode stage, the instruction is fetched from memory, and the operands needed for the instruction are identified. The operands are then fetched from the register file or memory. The information about the operation to be performed and the operands is then passed on to the next stage, which is often the Execute (ALU) stage.

In the Execute stage, the actual computation, or operation, is performed on the fetched operands. Therefore, the operand fetching, where the values are obtained from registers or memory, usually occurs in the Instruction Decode stage.

 

 

 

 

Answer 1

In a Classic RISC pipeline having only 1)Instruction fetch, 2)Instruction decode, and 3)Execute stages the operand is fetched in the instruction decode stage ,as in this stage only the effective address of operand is decoded and thus operand is fetched.

Whereas in the execute stage the operation is performed on the operands fetched in the decode stage.

Thus the operand fetching through the obtained effective address of the operand usuallly occurs in the Instruction Decode Stage.

Answer 2

In a Classic RISC pipeline having only 1)Instruction fetch, 2)Instruction decode, and 3)Execute stages the operand is fetched in the instruction decode stage ,as in this stage only the effective address of operand is decoded and thus operand is fetched.

Whereas in the execute stage the operation is performed on the operands fetched in the decode stage.

Thus the operand fetching through the obtained effective address of the operand occurs in the Instruction Decode Stage.