Login
Register
@
Dark Mode
Profile
Edit my Profile
Messages
My favorites
Register
Activity
Q&A
Questions
Unanswered
Tags
Subjects
Users
Ask
Previous Years
Blogs
New Blog
Exams
Dark Mode
Recent questions tagged machine-instruction
22
votes
2
answers
91
GATE CSE 1994 | Question: 3.2
State True or False with one line explanation Expanding opcode instruction formats are commonly employed in RISC. (Reduced Instruction Set Computers) machines.
Kathleen
asked
in
CO and Architecture
Oct 4, 2014
by
Kathleen
4.7k
views
gate1994
co-and-architecture
machine-instruction
instruction-format
normal
true-false
49
votes
6
answers
92
GATE CSE 2014 Set 1 | Question: 9
A machine has a $32\text{-bit}$ architecture, with $1\text{-word}$ long instructions. It has $64$ registers, each of which is $32$ bits long. It needs to support $45$ instructions, which have an immediate operand in ... to two register operands. Assuming that the immediate operand is an unsigned integer, the maximum value of the immediate operand is ____________
go_editor
asked
in
CO and Architecture
Sep 26, 2014
by
go_editor
18.3k
views
gatecse-2014-set1
co-and-architecture
machine-instruction
instruction-format
numerical-answers
normal
22
votes
3
answers
93
GATE CSE 1999 | Question: 17
Consider the following program fragment in the assembly language of a certain hypothetical processor. The processor has three general purpose registers $R1, R2$and $R3$. The meanings of the instructions are shown by comments (starting with ;) after the instructions. ... the values n, 0, and 0 respectively. What is the final value of $R3$ when control reaches $Z$?
Kathleen
asked
in
CO and Architecture
Sep 23, 2014
by
Kathleen
5.9k
views
gate1999
co-and-architecture
machine-instruction
normal
descriptive
47
votes
6
answers
94
GATE CSE 2005 | Question: 79
Consider the following data path of a $\text{CPU}.$ The $\text{ALU},$ the bus and all the registers in the data path are of identical size. All operations including incrementation of the $\text{PC}$ and the $\text{GPRs}$ are to be carried out in the ... $2$ $3$ $4$ $5$
Kathleen
asked
in
CO and Architecture
Sep 22, 2014
by
Kathleen
24.3k
views
gatecse-2005
co-and-architecture
machine-instruction
data-path
normal
54
votes
5
answers
95
GATE CSE 2007 | Question: 71
Consider the following program segment. Here $\text{R1, R2}$ and $\text{R3}$ ... word addressable. The number of memory references for accessing the data in executing the program completely is $10$ $11$ $20$ $21$
Kathleen
asked
in
CO and Architecture
Sep 21, 2014
by
Kathleen
22.1k
views
gatecse-2007
co-and-architecture
machine-instruction
interrupts
normal
54
votes
7
answers
96
GATE CSE 2007 | Question: 54
In a simplified computer the instructions are: ... computation should be in memory. What is the minimum number of MOV instructions in the code generated for this basic block? $2$ $3$ $5$ $6$
Kathleen
asked
in
CO and Architecture
Sep 21, 2014
by
Kathleen
13.4k
views
gatecse-2007
co-and-architecture
machine-instruction
normal
70
votes
4
answers
97
GATE CSE 2004 | Question: 63
Consider the following program segment for a hypothetical CPU having three user registers $R_1, R_2$ and $R_3.$ ... after executing the HALT instruction, the return address (in decimal) saved in the stack will be $1007$ $1020$ $1024$ $1028$
Kathleen
asked
in
CO and Architecture
Sep 18, 2014
by
Kathleen
29.0k
views
gatecse-2004
co-and-architecture
machine-instruction
normal
35
votes
3
answers
98
GATE CSE 2003 | Question: 48
Consider the following assembly language program for a hypothetical processor $A, B,$ and $C$ are $8-$ ... the program execution will be the number of $0$ bits in $A_0$ the number of $1$ bits in $A_0$ $A_0$ $8$
Kathleen
asked
in
CO and Architecture
Sep 17, 2014
by
Kathleen
15.0k
views
gatecse-2003
co-and-architecture
machine-instruction
normal
41
votes
11
answers
99
GATE CSE 2006 | Question: 09, ISRO2009-35
A CPU has $24$-$bit$ instructions. A program starts at address $300$ (in decimal). Which one of the following is a legal program counter (all values in decimal)? $400$ $500$ $600$ $700$
Rucha Shelke
asked
in
CO and Architecture
Sep 16, 2014
by
Rucha Shelke
16.0k
views
gatecse-2006
co-and-architecture
machine-instruction
easy
isro2009
54
votes
11
answers
100
GATE CSE 2001 | Question: 2.13
Consider the following data path of a simple non-pipelined CPU. The registers $A, B$, $A_{1},A_{2}, \textsf{MDR},$ the $\textsf{bus}$ and the $\textsf{ALU}$ are $8$-$bit$ wide. $\textsf{SP}$ and $\textsf{MAR}$ are $16$-$bit$ registers. The ... $\textsf{CPU}$ clock cycles are required to execute the "push r" instruction? $2$ $3$ $4$ $5$
Kathleen
asked
in
CO and Architecture
Sep 14, 2014
by
Kathleen
21.2k
views
gatecse-2001
co-and-architecture
data-path
machine-instruction
normal
42
votes
4
answers
101
GATE CSE 1992 | Question: 01-vi
In an $11$-bit computer instruction format, the size of address field is $4$-bits. The computer uses expanding OP code technique and has $5$ two-address instructions and $32$ one-address instructions. The number of zero-address instructions it can support is ________
Kathleen
asked
in
CO and Architecture
Sep 12, 2014
by
Kathleen
13.1k
views
gate1992
co-and-architecture
machine-instruction
instruction-format
normal
numerical-answers
41
votes
3
answers
102
GATE CSE 2008 | Question: 34
Which of the following must be true for the RFE (Return From Exception) instruction on a general purpose processor? It must be a trap instruction It must be a privileged instruction An exception cannot be allowed to occur during execution of an RFE instruction I only II only I and II only I, II and III only
Kathleen
asked
in
CO and Architecture
Sep 12, 2014
by
Kathleen
11.9k
views
gatecse-2008
co-and-architecture
machine-instruction
normal
Page:
« prev
1
2
3
4
Subscribe to GATE CSE 2024 Test Series
Subscribe to GO Classes for GATE CSE 2024
Quick search syntax
tags
tag:apple
author
user:martin
title
title:apple
content
content:apple
exclude
-tag:apple
force match
+apple
views
views:100
score
score:10
answers
answers:2
is accepted
isaccepted:true
is closed
isclosed:true
Recent Posts
Post GATE 2024 Guidance [Counseling tips and resources]
GATE CSE 2024 Result Responses
[Project Contest] Pytorch backend support for MLCommons Cpp Inference implementation
Participating in MLCommons Inference v4.0 submission (deadline is February 23 12pm IST)
IIITH PGEE 2024 Test Series by GO Classes
Subjects
All categories
General Aptitude
(3.5k)
Engineering Mathematics
(10.4k)
Digital Logic
(3.6k)
Programming and DS
(6.2k)
Algorithms
(4.8k)
Theory of Computation
(6.9k)
Compiler Design
(2.5k)
Operating System
(5.2k)
Databases
(4.8k)
CO and Architecture
(4.0k)
Computer Networks
(4.9k)
Artificial Intelligence
(79)
Machine Learning
(48)
Data Mining and Warehousing
(25)
Non GATE
(1.4k)
Others
(2.7k)
Admissions
(684)
Exam Queries
(1.6k)
Tier 1 Placement Questions
(17)
Job Queries
(80)
Projects
(11)
Unknown Category
(870)
64.3k
questions
77.9k
answers
244k
comments
80.0k
users
Recent questions tagged machine-instruction
Recent Blog Comments
category ?
Hi @Arjun sir, I have obtained a score of 591 in ...
download here
Can you please tell about IIT-H mtech CSE self...
Please add your admission queries here:...