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Recent questions tagged machine-instruction
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61
Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 3
A processor is having an instruction which can move a string of Bytes from one memory location to another. The fetching and decoding of the instruction takes $10$ clock cycles. To transfer each Byte ... instruction can transfer a string of $64$ Bytes then to execute the instruction, time required is ________ns
Bikram
asked
in
CO and Architecture
May 27, 2017
by
Bikram
393
views
tbb-coa-2
numerical-answers
computer-architecture
machine-instruction
4
votes
2
answers
62
gatebook mt2 qn-36
Consider a simple in-order five-stage pipeline with a two-cycle branch misprediction penalty and a single-cycle load-use delay penalty. For a specific program, 30% of the instructions are loads, 20% are branches, the remaining 50% of instructions are ... dependent instruction, and 75% of branches are predicted correctly. What is the average CPI of this program on this processor?
Purple
asked
in
CO and Architecture
Feb 7, 2017
by
Purple
1.8k
views
co-and-architecture
machine-instruction
clock-frequency
4
votes
1
answer
63
gatebook mt2
A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations. ADD Rs1, Rs2, Rd /* Add Rs1 to Rs2 and put the sum in Rd */ MUL Rs1, Rs2, Rd /* Multiply Rs1 by Rs2 and put the product in Rd */ An operation ... of clock cycles required for an operation sequence that computes the value of AB + ABC + BC ? (A) 5 (B) 6 (C) 7 (D) 8
Purple
asked
in
CO and Architecture
Feb 7, 2017
by
Purple
2.7k
views
machine-instruction
co-and-architecture
clock-frequency
1
vote
1
answer
64
Test by Bikram | Mock GATE | Test 2 | Question: 49
Consider the following sequence of instructions intended for execution on a stack machine. Each arithmetic operation pops the second operand, then pops the first operand, operates on them, and then pushes the result back onto the stack. Push b Push x Add ... of execution, the stack is empty. I and III only II and III only II only I, II, and III
Bikram
asked
in
GATE
Jan 24, 2017
by
Bikram
868
views
tbb-mockgate-2
computer-architecture
cpu
machine-instruction
3
votes
1
answer
65
Test by Bikram | Mock GATE | Test 1 | Question: 53
A computer uses a memory unit with $512K$ words of $64$ bits each. A binary instruction code is stored in one word of memory. The instruction has four parts: an indirect bit, an operation code, a register code part (to specify one of $256$ registers), and an address part. The number of bits in the operation code are _______.
Bikram
asked
in
GATE
Jan 16, 2017
by
Bikram
925
views
tbb-mockgate-1
numerical-answers
machine-instruction
co-and-architecture
7
votes
3
answers
66
GATE CSE 1988 | Question: 9i
The following program fragment was written in an assembly language for a single address computer with one accumulator register: LOAD B MULT C STORE T1 ADD A STORE T2 MULT T2 ADD T1 STORE Z Give the arithmetic expression implemented by the fragment.
go_editor
asked
in
CO and Architecture
Dec 19, 2016
by
go_editor
1.7k
views
gate1988
normal
descriptive
co-and-architecture
machine-instruction
20
votes
2
answers
67
Expanding opcode technique
A CPU is designed to have 58 three-address instructions and 25 two-address instructions. The CPU is able to address a maximum of 16 memory locations. The length of machine code is the same for all instructions. If the list of the ... of twoaddress instructions iv) Determine the length of the machine code v) List the machine codes Detailed explanation would be helpful
Prajwal Bhat
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in
CO and Architecture
Dec 10, 2016
by
Prajwal Bhat
10.8k
views
co-and-architecture
machine-instruction
2
votes
2
answers
68
Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 21
In a computer system, there are $5$ registers, namely -- $PC, AR, DR, IR,$ and $SC$. The initial content of $PC$ is $7FF$. The content of memory at address $7FF$ is $EA9F$; at address $A9F$ is ... and executed, the content of $PC$ register after $6$ clock pulse is ________ (put the integer value of register content).
Bikram
asked
in
CO and Architecture
Nov 25, 2016
by
Bikram
1.7k
views
tbb-coa-1
co-and-architecture
machine-instruction
numerical-answers
0
votes
1
answer
69
Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 12
A computer uses a small direct-mapped cache between the main memory and the processor. The cache has four $16$-bit words (the data field), and each word has an associated $13$-bit tag field. When a miss occurs during a read ... number of Main memory access at the end of the First pass through the loop? $3$ $4$ $6$ $8$
Bikram
asked
in
CO and Architecture
Nov 25, 2016
by
Bikram
523
views
tbb-coa-1
co-and-architecture
machine-instruction
1
vote
2
answers
70
Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 10
Registers $R1$ and $R2$ of a computer contain the decimal values $1300$ and $4500$. The following instructions are run: $\text{ Load 20(R1),R5}$ $\text{Move #3000,R5}$ $\text{Store R5,30(R1,R2)}$ The effective address of the memory operand is ___________.
Bikram
asked
in
CO and Architecture
Nov 25, 2016
by
Bikram
748
views
tbb-coa-1
co-and-architecture
machine-instruction
numerical-answers
5
votes
1
answer
71
MadeEasy Workbook: CO & Architecture - Machine Instructions
In the program below, the number of times the FIRST and SECOND JNZ instructions cause the control to be transferred to LOOP respectively MVI H, 02H MVI L, 05H LOOP: DCR L ; Decrement L by 1 FIRST: JNZ LOOP DCR H SECOND: JNZ LOOP 5 and 2 4 and 1 259 and 1 260 and 1
Shubham Sharma 2
asked
in
CO and Architecture
Aug 27, 2016
by
Shubham Sharma 2
1.4k
views
made-easy-test-series
co-and-architecture
machine-instruction
3
votes
2
answers
72
UGC NET CSE | December 2015 | Part 2 | Question: 42
What will be the hexadecimal value in the register $ax$ (32-bit) after executing the following instructions? mov al, 15 mov ah, 15 xor al, al mov cl, 3 shr ax, cl 0F00 h 0F0F h 01E0 h FFFF h
go_editor
asked
in
Compiler Design
Aug 8, 2016
by
go_editor
8.9k
views
ugcnetcse-dec2015-paper2
machine-instruction
compiler-design
3
votes
2
answers
73
ISRO2008-42
Which of the following architecture is/are not suitable for realising SIMD? Vector processor Array processor Von Neumann All of the above
go_editor
asked
in
CO and Architecture
Jun 12, 2016
by
go_editor
4.8k
views
isro2008
co-and-architecture
machine-instruction
9
votes
2
answers
74
ISI2011-PCB-CS-6a
Assume a machine has $4$ registers (one of which is the accumulator $A$) and the following instruction set. $\text{LOAD}$ and $\text{STORE}$ are indirect memory operations that load and store, using the address stored in the given register operand ... . Design an instruction encoding scheme that allows each of the above instructions (along with operands) to be encoded in $8$ bits.
go_editor
asked
in
CO and Architecture
Jun 3, 2016
by
go_editor
1.3k
views
co-and-architecture
descriptive
isi2011-pcb-cs
machine-instruction
29
votes
3
answers
75
GATE CSE 2003 | Question: 49
Consider the following assembly language program for a hypothetical processor $A, B,$ and $C$ are $8$ bit registers. The meanings of various instructions are shown as comments. MOV B, #0 ; $B \leftarrow 0$ MOV C, #8 ; $C \leftarrow 8$ Z: CMP C, #0 ; compare C ... $\text{LRC A,} \#1; $ left rotate $A$ through carry flag by one bit $\text{ADD A,} \#1$
go_editor
asked
in
CO and Architecture
Apr 24, 2016
by
go_editor
9.8k
views
gatecse-2003
co-and-architecture
machine-instruction
normal
59
votes
4
answers
76
GATE CSE 2004 | Question: 64
Consider the following program segment for a hypothetical CPU having three user registers $R_1, R_2$ and $R_3.$ ... }\\\hline \end{array} The total number of clock cycles required to execute the program is $29$ $24$ $23$ $20$
go_editor
asked
in
CO and Architecture
Apr 24, 2016
by
go_editor
19.6k
views
gatecse-2004
co-and-architecture
machine-instruction
normal
55
votes
12
answers
77
GATE CSE 2005 | Question: 80
Consider the following data path of a $\text{CPU}.$ The $\text{ALU},$ the bus and all the registers in the data path are of identical size. All operations including incrementation of the $\text{PC}$ and the $\text{GPRs}$ are to be carried out in ... $2$ $3$ $4$ $5$
go_editor
asked
in
CO and Architecture
Apr 24, 2016
by
go_editor
24.2k
views
co-and-architecture
normal
gatecse-2005
data-path
machine-instruction
30
votes
2
answers
78
GATE CSE 2007 | Question: 73
Consider the following program segment. Here $\text{R1, R2}$ and $\text{R3}$ ... the execution of the instruction INC R3 , what return address will be pushed on to the stack? $1005$ $1020$ $1024$ $1040$
go_editor
asked
in
CO and Architecture
Apr 23, 2016
by
go_editor
9.9k
views
gatecse-2007
co-and-architecture
machine-instruction
interrupts
normal
35
votes
5
answers
79
GATE CSE 2007 | Question: 72
Consider the following program segment. Here $\text{R1, R2}$ and $\text{R3}$ ... is word addressable. After the execution of this program, the content of memory location $2010$ is: $100$ $101$ $102$ $110$
go_editor
asked
in
CO and Architecture
Apr 23, 2016
by
go_editor
9.4k
views
gatecse-2007
co-and-architecture
machine-instruction
interrupts
normal
67
votes
4
answers
80
GATE CSE 2016 Set 2 | Question: 31
Consider a processor with $64$ registers and an instruction set of size twelve. Each instruction has five distinct fields, namely, opcode, two source register identifiers, one destination register identifier, and twelve-bit immediate value. Each ... program has $100$ instructions, the amount of memory (in bytes) consumed by the program text is _________.
Akash Kanase
asked
in
CO and Architecture
Feb 12, 2016
by
Akash Kanase
20.9k
views
gatecse-2016-set2
instruction-format
machine-instruction
co-and-architecture
normal
numerical-answers
29
votes
5
answers
81
GATE CSE 2016 Set 2 | Question: 10
A processor has $40$ distinct instruction and $24$ general purpose registers. A $32$-bit instruction word has an opcode, two registers operands and an immediate operand. The number of bits available for the immediate operand field is_______.
Akash Kanase
asked
in
CO and Architecture
Feb 12, 2016
by
Akash Kanase
13.6k
views
gatecse-2016-set2
machine-instruction
co-and-architecture
easy
numerical-answers
13
votes
5
answers
82
ISRO2015-77
In $\text{X = (M + N }\times \text{O)/(P} \times \text{Q})$, how many one-address instructions are required to evaluate it? $4$ $6$ $8$ $10$
Purple
asked
in
CO and Architecture
Jan 26, 2016
by
Purple
7.0k
views
memory-interfacing
co-and-architecture
machine-instruction
isro2015
3
votes
0
answers
83
Differencee Between DCR and DCRL Instruction.
Want to know difference between : DCR and DCRL SUB and SUBL
kartikey
asked
in
CO and Architecture
Nov 29, 2015
by
kartikey
504
views
machine-instruction
12
votes
3
answers
84
Max number of one address instruction, when two address instruction is given is?
A computer uses expanding opcode. It has 16 bit instructions 6 bit addresses, it supports one address, two address instructions only. If there are n two address instructions, the maximum number of one address instructions are?
Tehreem
asked
in
CO and Architecture
Sep 9, 2015
by
Tehreem
11.7k
views
co-and-architecture
addressing-modes
machine-instruction
instruction-format
3
votes
2
answers
85
consider a hypothetical processor which support both 1 address and zero address instruction.
Consider a hypothetical processor which support both 1 address and zero address instruction. It contain 6 bit instruction and four bit address if there exists 2 one address instruction than how many zero address instruction can be formulated?
focus _GATE
asked
in
CO and Architecture
Jun 5, 2015
by
focus _GATE
5.5k
views
co-and-architecture
machine-instruction
57
votes
3
answers
86
GATE CSE 2015 Set 2 | Question: 42
Consider a processor with byte-addressable memory. Assume that all registers, including program counter (PC) and Program Status Word (PSW), are size of two bytes. A stack in the main memory is implemented from memory location $(0100)_{16}$ and it grows upward. The stack ... value of the stack pointer is: $(016A)_{16}$ $(016C)_{16}$ $(0170)_{16}$ $(0172)_{16}$
go_editor
asked
in
CO and Architecture
Feb 12, 2015
by
go_editor
16.9k
views
gatecse-2015-set2
co-and-architecture
machine-instruction
easy
31
votes
1
answer
87
GATE IT 2004 | Question: 46
If we use internal data forwarding to speed up the performance of a CPU (R1, R2 and R3 are registers and M[100] is a memory reference), then the sequence of operations R1 → M[100] M[100] → R2 M[100] → R3 can be replaced by R1 → R3 R2 → M[100] M[100] → R2 R1 → R2 R1 → R3 R1 → M[100] R2 → R3 R1 → R2 R1 → R3 R1 → M[100]
Ishrat Jahan
asked
in
CO and Architecture
Nov 2, 2014
by
Ishrat Jahan
6.8k
views
gateit-2004
co-and-architecture
machine-instruction
easy
56
votes
5
answers
88
GATE IT 2007 | Question: 41
Following table indicates the latencies of operations between the instruction producing the result and instruction using the result. ... to execute the above code segment assuming each instruction takes one cycle to execute? $7$ $10$ $13$ $14$
Ishrat Jahan
asked
in
CO and Architecture
Oct 29, 2014
by
Ishrat Jahan
22.7k
views
gateit-2007
co-and-architecture
machine-instruction
normal
38
votes
5
answers
89
GATE IT 2008 | Question: 38
Assume that EA = (X)+ is the effective address equal to the contents of location X, with X incremented by one word length after the effective address is calculated; EA = −(X) is the effective address equal to the contents of location X, with X decremented by one word length before the ... back to the stack. ADD (X)−, (X) ADD (X), (X)− ADD −(X), (X)+ ADD −(X), (X)
Ishrat Jahan
asked
in
CO and Architecture
Oct 28, 2014
by
Ishrat Jahan
8.9k
views
gateit-2008
co-and-architecture
machine-instruction
normal
21
votes
4
answers
90
GATE CSE 1994 | Question: 12
Assume that a CPU has only two registers $R_1$ and $R_2$ and that only the following instruction is available $XOR \: R_i, R_j;\{R_j \leftarrow R_i \oplus R_j, \text{ for } i, j =1, 2\}$ Using this XOR instruction, find an instruction sequence in ... and $R_2$ The line p of the circuit shown in figure has stuck at $1$ fault. Determine an input test to detect the fault.
Kathleen
asked
in
CO and Architecture
Oct 5, 2014
by
Kathleen
3.8k
views
gate1994
co-and-architecture
machine-instruction
normal
descriptive
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