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GATE 2019
What will be the answer to this question ? Will it go in infinite loop ?
commented
in
Digital Logic
Feb 4, 2019
1.3k
views
usergate2019
usermod
2
answers
2
gate 2019
commented
in
Digital Logic
Feb 3, 2019
1.7k
views
1
answer
3
Gate 19
The expenditure ______ as follows ...… Break down or breaks down
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in
Verbal Aptitude
Feb 3, 2019
2.6k
views
1
answer
4
Minor Clarifications
OS: Which process scheduling mechanism gives the optimal average waiting time and throughput, is it SJF or SRTF? Which DISK scheduling algo gives the minimum seek time is it SSTF?
asked
in
Operating System
Feb 2, 2019
394
views
scheduling
0
answers
5
Previous gate
asked
in
Linear Algebra
Jan 31, 2019
351
views
eigen-value
0
answers
6
Number of Comparisons
Consider the following code segment: int j, k,n; for(j=1;j<=n-1;j++){ for(k=j+1;k<n;k++){ if(A[j]> A[k]){ A[j]=A[j+2]; } } } (Where n is the size of array A[ ] and starting index is 1) Number of comparison made by the above code when n = 84 ________. given answer is 84*83/2 =3486 shouldn’t it be 83*82/2 = 3403
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in
Programming in C
Jan 30, 2019
629
views
programming-in-c
programming
1
answer
7
MadeEasy Test Series 2019: Algorithms - Spanning Tree
Consider a simple undirected weighted graph G(V, E) with 10 vertices and 45 edge, assume (u, v) are two vertices weight of a edge is =4lu- vl then the minimum cost of the spanning tree of G_ 36
commented
in
Algorithms
Jan 30, 2019
1.6k
views
algorithms
spanning-tree
minimum-spanning-tree
made-easy-test-series
numerical-answers
3
answers
8
GATE CSE 2001 | Question: 8
Consider a disk with the following specifications: 20 surfaces, 1000 tracks/surface, 16 sectors/track, data density 1 KB/sector, rotation speed 3000 rpm. The operating system initiates the transfer between the disk and the memory sector-wise. Once the head ... What is the maximum percentage of time the CPU is held up for this disk I/O for cycle-stealing DMA transfer?
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in
Operating System
Jan 29, 2019
10.1k
views
gatecse-2001
operating-system
disk
normal
descriptive
4
answers
9
GATE CSE 2017 Set 1 | Question: 21
Consider the Karnaugh map given below, where $X$ represents "don't care" and blank represents $0$. Assume for all inputs $\left ( a,b,c,d \right )$ ... . The above logic is implemented using $2$-input $\text{NOR}$ gates only. The minimum number of gates required is ____________ .
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in
Digital Logic
Jan 29, 2019
14.1k
views
gatecse-2017-set1
digital-logic
k-map
numerical-answers
normal
6
answers
10
GATE CSE 2000 | Question: 2.11
Which functions does NOT implement the Karnaugh map given below? $(w + x) y$ $xy + yw$ $(w + x) (\bar{w} + y) (\bar{x} + y)$ None of the above
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in
Digital Logic
Jan 29, 2019
7.1k
views
gatecse-2000
digital-logic
k-map
normal
2
answers
11
GATE CSE 2001 | Question: 11
A sequential circuit takes an input stream of $0's$ and $1's$ and produces an output stream of $0's$ and $1's.$ Initially it replicates the input on its output until two consecutive $0's$ are encountered on the input. From then ... Give the minimized sum-of-product expression for $\text{J}$ and $\text{K}$ inputs of one of its state flip-flops
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in
Digital Logic
Jan 29, 2019
5.2k
views
gatecse-2001
digital-logic
normal
descriptive
flip-flop
1
answer
12
ACE CBT 2018
An instruction pipelined processor has five stages namely, instruction fetch (F), instruction decode (D), Instruction execution (E), memory Access for operand (M) and write Back (W) with stage latencies of 1 ns, 2ns, 2 ns, 1 ns, 1 ns respectively. To gain ... (in ns) using new design over old design is __________. I am getting 99 but the answer provided is 96. Can you please verify.
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in
CO and Architecture
Jan 28, 2019
619
views
co-and-architecture
cbt-2018
pipelining
1
answer
13
ACE Test series Question on CFG
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in
Compiler Design
Jan 24, 2019
639
views
compiler-design
grammar
context-free-grammar
ace-test-series
0
answers
14
#selfdoubt
R2(X) R2(Y) R1(X) R1(Y) W1(X) R2(X) R2(X) R2(Y) R1(X) R1(Y) W1(X) R1(X) R2(X) R2(Y) R1(X) R1(Y) W1(X) commit(t1) R2(X) Which of the above have unrepeatable read problem?
asked
in
Databases
Jan 24, 2019
195
views
schedules-dbms
0
answers
15
NPTEL assignment
A DMA controller transfers 32-bit words from an input device to memory in one clock cycle using cycle stealing. The input device transmits data at a rate of 9600 bytes per second. The CPU is fetching and executing instructions at an average rate of 2,000,000 instructions ... the DMA transfer by .. percent. I am getting 0.12 as the answer but they have given 0.24 please check
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in
CO and Architecture
Jan 24, 2019
950
views
co-and-architecture
dma
1
answer
16
MeTest-BST
When searching for the key value 50 in the binary search tree, node containing the key values 10,30,40,70,90,120,150,175 are traversed in any order.The number of different orders possible in which these keys values can occur on the search path from root to the node containing the value 50 are?
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in
Programming in C
Jan 24, 2019
628
views
data-structures
0
answers
17
RUN TIME error
why this program given run time error #include<stdio.h> int main ( ) { int x = 2, y = 5; if (x < y) return (x = x+y); else printf(“%d “,x); printf(“%d”,y); } https://ideone.com/AqYv40
commented
in
Programming in C
Jan 23, 2019
345
views
programming-in-c
easy
0
answers
18
TestBook_FLT
A data is sent to UDP,along with a pair of socket address and the length of the data.After receiving data,UDP adds the header and passes the UDP datagram to IP.What is the maximum size of the payload that can be encapsulated in a UDP datagram, to avoid fragmentation. ... $1500-20-8=1472\,Bytes$ But Answer is given to be $65507$ I know how that figure came but my question is Why that?
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in
Computer Networks
Jan 23, 2019
411
views
computer-networks
3
answers
19
GATE IT 2008 | Question: 69
The three way handshake for $\text{TCP}$ connection establishment is shown below. Which of the following statements are TRUE? $S1:$ Loss of $\text{SYN} + \text{ACK}$ from the server will not establish a connection $S2:$ Loss of $\text{ACK}$ from the client cannot establish ... on no packet loss $S2$ and $S3$ only $S1$ and $S4$ only $S1$ and $S3$ only $S2$ and $S4$ only
commented
in
Computer Networks
Jan 21, 2019
15.2k
views
gateit-2008
computer-networks
tcp
normal
1
answer
20
processor performance
insufficient info p2 p1
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in
CO and Architecture
Jan 14, 2019
681
views
co-and-architecture
1
answer
21
me test
Consider the basic block given below: u=u+v v=v+w x=v-w y=v-x z=u+v The minimum number of nodes and edges present in the DAG representations of the above basic block respectively are:
commented
in
Compiler Design
Jan 12, 2019
1.3k
views
compiler-design
code-optimization
directed-acyclic-graph
numerical-answers
0
answers
22
Self doubt
11^23 mod 187= 149 by using virtual gate calculator... plz tell me where i am wrong...??
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in
Computer Networks
Jan 12, 2019
1.3k
views
see-later
0
answers
23
prime Imp
Consider the function f(P,Q,R,S)=Σ(0,5,7,8,10,13,15) + Σd(1,2,3,9). The number of prime implicants for the function is
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in
Digital Logic
Jan 4, 2019
585
views
digital-logic
prime-implicants
1
answer
24
Recurrence relation
T(n) = T(n/4) + T(3n/4) + n How to solve these type of problems? Can I solve this using master theorm by considering X = T(3N/4) +N THEN T(N) = T(N/4) +X CAN WE SOLVE LIKE THIS? PLEASE HELP
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in
Algorithms
Jan 4, 2019
1.3k
views
recurrence-relation
time-complexity
algorithms
1
answer
25
Digital Logic madeeasy
A 4 bit right shift register is shifting the data to the right for every clock pulse. The serial input D is derived by using XOR gates as shown. After 3 clock pulses the content in the register is to be 1010 at Q0Q1Q2Q3. What were the initial contents of the register? 1100 1010 0011 0101 I’m getting the answer as 0101 but it’s given 0011
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in
Digital Logic
Jan 4, 2019
2.0k
views
digital-logic
sequential-circuit
shift-registers
1
answer
26
Gb7 protocol
A link has transmission speed of 500*10^6 bps and one way prob delay of 2sec.If data pacjet size is 10^7 bits then efficiency of Gb7 is % Anyone getting 3.48 answer given is 63.18
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in
Computer Networks
Jan 4, 2019
281
views
4
answers
27
GATE IT 2005 | Question: 75
In a TDM medium access control bus LAN, each station is assigned one time slot per cycle for transmission. Assume that the length of each time slot is the time to transmit $100$ $\text{bits}$ ... in the LAN so that the throughput of each station can be $2/3$ $\text{Mbps}$ is $3$ $5$ $10$ $20$
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in
Computer Networks
Jan 3, 2019
14.1k
views
gateit-2005
computer-networks
mac-protocol
normal
0
answers
28
Clarification on Topic
In the syllabus it was said “differentiability” does this mean we have partial differentiation.??
commented
in
Calculus
Jan 2, 2019
340
views
general-query
2
answers
29
Stack implementation by using queue
true/false ? ) if stack is implemented as a array,all operation push ,pop ,is emptystack(),delete stack() can be performed in constant time. )if stack is implemented as a linked list ,all operation ,is emptystack(),delete stack() can be performed in constant time.
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in
Programming in C
Jan 2, 2019
1.4k
views
data-structures
queue
stack
9
answers
30
GATE CSE 2015 Set 2 | Question: 52
$\text{Host A}$ sends a $\text{UDP}$ datagram containing $8880\text{ bytes}$ of user data to $\text{host B}$ over an $\text{Ethernet LAN}.$ Ethernet frames may carry data up to $1500\text{ bytes (i.e. MTU = 1500 bytes)}.$ Size of $\text{UDP}$ ... be the contents of offset field in the last fragment? $6$ and $925$ $6$ and $7400$ $7$ and $1110$ $7$ and $8880$
commented
in
Computer Networks
Jan 2, 2019
25.6k
views
gatecse-2015-set2
computer-networks
ip-packet
normal
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