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1
vote
1
NIELIT 2016 DEC Scientist B (CS) - Section B: 20
Bluetooth is an example of: Personal area network Virtual private network Local area network None of the above
answered
in
Computer Networks
Aug 9, 2020
701
views
nielit2016dec-scientistb-cs
computer-networks
0
votes
2
made easy test series
please provide a detailed solution
answered
in
CO and Architecture
Aug 9, 2020
606
views
co-and-architecture
cache-memory
1
vote
3
NIELIT 2017 DEC Scientist B - Section B: 14
We have $10$-stage pipeline, where the branch target conditions are resolved at stage $5$. How many stalls are there for an incorrectly predicted branch? $5$ $6$ $7$ $4$
answered
in
CO and Architecture
Aug 2, 2020
1.9k
views
nielit2017dec-scientistb
co-and-architecture
pipelining
0
votes
4
NIELIT 2017 DEC Scientist B - Section B: 13
Consider a non-pipelined machine with $6$ stages; the lengths of each stage are $\text{20ns, 10ns, 30ns,25ns, 40 ns}$ and $\text{15ns}$ respectively. Suppose for implementing the pipelining the machine adds $\text{5 ns}$ of overhead to each stage ... What is the speed up factor of the pipelining system (ignoring any hazard impact)? $7$ $14$ $3.11$ $6.22$
answered
in
CO and Architecture
Aug 2, 2020
5.0k
views
nielit2017dec-scientistb
co-and-architecture
pipelining
0
votes
5
NIELIT 2017 July Scientist B (CS) - Section B: 28
For a memory system, the cycle time is Same as the access time. Longer than the access time. Shorter than the access time. Multiple of the access time.
answered
in
CO and Architecture
Aug 2, 2020
1.1k
views
nielit2017july-scientistb-cs
co-and-architecture
memory-interfacing
0
votes
6
NIELIT 2017 July Scientist B (CS) - Section B: 23
Comparing the time $T1$ taken for a single instruction on a pipelined CPU, with time $T2$ taken on a non-pipelined but identical CPU, we can say that ______ ? $T1=T2$ $T1>T2$ $T1<T2$ $T1$ is $T2$ plus time taken for one instruction fetch cycle
answered
in
CO and Architecture
Aug 2, 2020
1.1k
views
nielit2017july-scientistb-cs
co-and-architecture
pipelining
0
votes
7
NIELIT 2016 DEC Scientist B (CS) - Section B: 53
The addressing mode used in an instruction of the form $ADD\:X\:Y$, is Direct Absolute Indirect Indexed
answered
in
CO and Architecture
Aug 2, 2020
4.6k
views
nielit2016dec-scientistb-cs
co-and-architecture
addressing-modes
1
vote
8
NIELIT 2016 DEC Scientist B (IT) - Section B: 37
How many address lines are needed to address each memory location in a $2048\times4$ memory chip? $10$ $11$ $8$ $12$
answered
in
CO and Architecture
Aug 2, 2020
865
views
nielit2016dec-scientistb-it
co-and-architecture
memory-interfacing
0
votes
9
NIELIT 2016 MAR Scientist B - Section C: 9
A certain processor supports only the immediate and the direct addressing modes. Which of the following programming language features cannot be implemented on this processor? Pointers. Arrays. Records. All of these.
answered
in
CO and Architecture
Aug 2, 2020
1.8k
views
nielit2016mar-scientistb
co-and-architecture
addressing-modes
1
vote
10
nielit 2018 q52
Given a mask, M=255.255.255.248. How many subnet bits are required for given mask M? (A) 2 (B) 3 (C) 4 (D)5
answered
in
Computer Networks
Jul 30, 2020
1.9k
views
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