MadeEasy Subject Test: Digital Logic - Shift Registers

Question

Three 4 bit shift registers are connected in cascade as shown in figure below. Each register is applied with

A 4 bit data 1011 is applied to the shift register 1. What is the minimum number of clock pulses required to get same input data at output are with same clock?

Comments

@Lokesh . add it as answer. nice tabular format

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added

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@Lokesh . Isn't it true that SISO takes n i/p clk pulse and n-1 o/p clk pulse? Then how here we are taking total 8 clk cycles instead of just 7(4i/p +3o/p) ?

Answer 1

Clock	SISO	SIPO	PISO	Output
0	0000	0000	0000
1	1000	0000	0000
2	1100	0000	0000
3	0110	0000	0000
4	1011	0000	0000
5	0101	1000	0000
6	0010	1100	1000
7	0001	0110	1100	0
8	0000	1011	0110	0
9	0000	0101	1011	1
10	0000	0010	0101	11
11	0000	0001	0010	011
12	0000	0000	0001	1011

12 Clock Pulses is correct answer

Comments

@lokesh

regarding msb its my fault I was taking considering msb towards the right hand side I should have explained my convention

but going by your convention

in 8th cycle lsb is still 0

so output can''t be 1 in 9th cycle

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lsb of 9th cycle is output not 8th cycle

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@Akriti
all 3 registers are connected in a synchronous manner
so all registers are active at a time...so when SIPO generates output...that output will be available for PISO in the same cycle....but to take it as input PISO will require next cycle...internal structure is nothing but flip-flops