GATE ECE 2016

Question

For the circuit shown in the figure, the delay of the bubbled NAND gate is 2ns and that of the
counter is assumed to be zero.

If the clock (Clk) frequency is 1GHz, then the counter behaves as a:
(A) mod-5 counter

(B) mod-6 counter

(C) mod-7 counter

(D) mod-8 counter
What is approach applied for such type of question????

Comments

Mod 7 counter

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can u plz upload ur detailed ans?

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im too getting mod 9.

Answer 1

As it is a 3 bit synchronous counter the no of states should be 8.

But we have to see the clear input

q2 q1 q0

1    1   0     this is applied to nand gate     ( it seems that it's mod 6 counter (state 0 to 5 ))and state 6 and 7 are connected to clear )

output is 1 or reset is 1

complement (reset)=0 hence no clear signal to the flipflop

so it's a mod 8 counter.