What is the best architecture of the ‘Logic gate’?
its up counter , in 4th clock pulse, we need to make Q3 bit as 0 in order to get mod 4 counter. so, NOT gate is required as clear inputs are active low.
as this is asynchronous circuit Q0n= Q0' for every signal
Q1n= Q1' (for Q0 1->0 transaction as its negative edge trigger )
Q2n=Q2' (for Q1 1->0)
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