@prateek bro i got the explanation that why it is happening,tell me one more thing ,you said that after instruction decode while fecthing the oprerand then only get to know that it is depending on previous thats why OF stage have to wait untill operand not available , and thats's why ,you introduced 3 stall in 4, 5 ,6 clock cycle, and similarly for I3 there will be dependency so you introduced 6 stall 5 to 10 clock cycle
i want to ask can our circuitry detect the dependency in ID statge itself ?
if it will detect in ID stage then also stall would be same and we would do OF after WB
please clear my it and if a said anything wrong then correct me