MadeEasy Test Series: CO & Architecture - Cache Memory

Question

consider a CPU contains 2000 instructions, there are 80 misses in L1 cache and 40 misses in the L2 cache. Assume miss penalty from the L2 cache to memory is 200 clock cycles, the hit time of L2 cache is 30 clock cycles, the hit time of L1 cache is 5 clock cycles and there are 1.8 memory references per instruction, then average stall per instruction is                  

1. 6.36
2. 7.92
3. 9.62
4. 9.35

Comments

this is the things, I told in an earlier comment.there should 2000 MR not 2000 instructions.

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in the case of 2000 instructions that is 3600 references answer will be 5.2

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there should 2000 MR not 2000 instructions.

it should be 2000 instructions only.

the answer is 9.36

you may check it on https://gateoverflow.in/281228/doubt-previous-year

@Shubhanshu

tag me correctly otherwise i didn't get notification.

Answer 1

Easiest solution would be:

calculate the total no of clocks without any miss = [ 2000(5) ]*1.8 = 18000

calculate the same with misses as given in the question = [ 2000(5)  + 80(30) + 40(200) ]*1.8 = 36720

stall cycle per instruction would be 36720 - 18000 / 2000 = 9.36

Comments

the answer will be 9.36 when 2000 references given but here references are 3600, so the answer is 5.2.

Answer 2

Average memory stall time per instruction  =  Average number of memory accesses per instruction * Average memory access time.

Assuming no memory stalls for $L_1$ hit

$L_1$ miss rate $=\frac{80}{2000 \times 1.8} =  \frac{1}{45}$

$L_2$ miss rate $= \frac{40}{80} = 0.5$

Therefore, Average memory stalls time per instruction

$\qquad =1.8 \times  (\frac{1}{45} \times (30 + 0.5 \times 200)$

$\qquad = 1.8 \times \left( \frac{130}{45}\right) = 5.2$ cycles

Comments

Sir, what is the need of considering stall in case of $L_1$ hit?

I think the answer should be $5.202$.

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@Arjun

Sir, here is a similar problem that is given in the book Computer Architecture- A Quantitative Approach 4th Edition, Hennessy Patterson

So according to the below problem, they haven't added the CPU Stalls on L1 hit. Isn't it?

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@Arjun

Sir, here is another text in the same book describing what exactly is memory stalls. Kindly go through and let me know whether to add the L1 part.

 

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@Fyse One small thing there is the $L_1$ hit time - given as 1 cycle. So it is safe to assume it is not causing a stall. But 5 cycles? Anyway it depends on how it is used/defined in the given question and should be clear in GATE. When such questions are given in Patterson not sure why people are posting ME ones here 😥