Set associative cache implementation

Question

Given the following specifications for an external cache memory: four-way set associative; line size of two 16-bit words; able to accommodate a total of 4K 32-bit words from main memory; used with a 16-bit processor that issues 24-bit addresses. Show how cache interprets the processor’s addresses.

Comments

TAG bits : 13 bits

set offset : 10 bits

word offset : 1 bit

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Does this given solution makes any sense to you? It gives: 12-10-2. I have doubt especially for that word and byte select. Only diagram was given. No explanation 😑😞

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I understood the diagram but what I don't understand is why they have an extra bit as byte select.

When physical address is given, its a reference to word not byte.

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yup same doubt