A CPU Manufacturer company has two designs p1 and p2 for a synchronous pipeline processor.
P1 has 5 pipeline stages with execution times of 3 ns, 4 ns, 3 ns, 2 ns, 4 ns while the design P2 has 6pipeline stage with 3 ns each (execution time).
The time that can be saved by P2 over P1 for executing 1000 Instructions is _____________ ns.
iam getting answer 997 but they give 1001
