in Digital Logic edited by
15,208 views
37 votes
37 votes

Which of the following input sequences will always generate a $1$ at the output $z$ at the end of the third cycle?

GATE2005-IT_43

  1. $\begin{array}{|l|l|}\hline \textbf{A} & \textbf{B} & \textbf{C} \\\hline  \text{0} & \text{0} & \text{0} \\\hline   \text{1} & \text{0} & \text{1} \\\hline  \text{1} & \text{1} & \text{1} \\\hline \end{array}$
  2. $\begin{array}{|l|l|}\hline \textbf{A} & \textbf{B} & \textbf{C} \\\hline  \text{1} & \text{0} & \text{1} \\\hline   \text{1} & \text{1} & \text{0} \\\hline  \text{1} & \text{1} & \text{1} \\\hline \end{array}$
  3. $\begin{array}{|l|l|}\hline \textbf{A} & \textbf{B} & \textbf{C} \\\hline  \text{0} & \text{1} & \text{1} \\\hline   \text{1} & \text{0} & \text{1} \\\hline  \text{1} & \text{1} & \text{1} \\\hline \end{array}$
  4. $\begin{array}{|l|l|}\hline \textbf{A} & \textbf{B} & \textbf{C} \\\hline  \text{0} & \text{0} & \text{1} \\\hline   \text{1} & \text{1} & \text{0} \\\hline  \text{1} & \text{1} & \text{1} \\\hline \end{array}$
in Digital Logic edited by
15.2k views

4 Comments

@Arjun sir, @Manu sir

Something is definitely wrong here, but if AND gate (Q’.C) is replaced by OR gate (Q’ + C), then we get option C as the correct answer.

Please verify this.
0
0
How in option A you got z=1?

$Z = Q_{0n} . Q_{1n}$

$Z = 1 . 0=0$
0
0
That was wrong. Thanks for pointing it out.
0
0

5 Answers

46 votes
46 votes
$${\begin{array}{|c|c|c|c|c|c|c|l|}\hline\\
\textbf{}&    \textbf{A}&  \textbf{B}&\bf{C}& \bf{Q_1}& \bf{Q_2} & \textbf{Z} & \textbf{Comment}\\\hline
\text{After } 1^{st} \text{Cycle} &\text{X} &\text{X} &\text{X} &\text{X} &\text{X} &\text{X} \\\hline \text{After } 2^{nd} \text{Cycle}&0&0&\text{X}&0&\text{X} & \text{X}& \text{$Q_1$ is 0 making A and B 0}\\ \hline    \text{After } 3^{rd} \text{Cycle}&\text{X} &\text{X} &1&1&1&1& \text{$Z$ is $1$ making $Q1$ and $Q2$ $1$,}\\&&&&&&&\text{Either $A$ or $B$ is $1$.} \\&&&&&&&\text{$Q1'$ of previous cycle is $1$.} \\ \hline
\end{array}}$$
The filling is done in reverse order. Here, none of the options match. So, something wrong somewhere.
edited by
by

4 Comments

Are this characteristic equations right ?

1
1
If you look at your explanation after 2nd clock if you give A=0 , B=0  then you will get Q1 = 0 at after 3rd cycle it doesn't make any  sense,

But if you give after 1st cycle A=0, B=0 then you will get after 2nd clock Q1=0 so the answer matched with the option A
0
0
edited by

@Arjun @gatecse @Deepak Poonia

 It can be concluded that A and B should be 0 for the second cycle and in the third clock cycle, either A or B or both has to be 1 and in the first clock cycle, we don't know the value of A and B.

→   After the 3rd clock cycle value of Z is 1 and after the 2nd clock cycle value of Z is 0 and after the 1st clock cycle, we don't know the value of Z.

Sir this picture is correct?

0
0
4 votes
4 votes
Answer is C

Explanation:

Here given in question first O/P Z is always 1 at the end of third cycle.

(I have consider first f/f Q as Q0 and second below f/f as Q1)

So Z=1

now for Z=1

Iff Q0 and Q1 are 1.

for Q0=1:

Either A or B should 1 or Both

i.e.

A B

0 1

1 0

1 1

Now for Q1=1:

Q0'.C=1   only when Q0=0 and C=1

Now combine the Input sequences(for both Q0=1 and Q1=1):

A B C

0 1 1

1 0 1

1 1 1

 

So, C is the Answer here.

2 Comments

Kindly check your logical implication again..
0
0
Yes,C is the correct answer.
0
0
2 votes
2 votes

I am getting  Option(a) as the correct answer. If wrong please rectify it.

I have taken the initial state as 0. 

2 Comments

check your x'
1
1
after applying clock 1, x and x' can't be same bcz after applying clock after sometime they must be different according to the circuit. so in this example all option should be wrong.
1
1
2 votes
2 votes
A B C $D_{top}$ $D_{bottom}$ $Q_{top}$ $Q_{bottom}$ Z Remark/Comment
X X X X X 1 1 1 Final Value
1 0 1 1 1 0 X X Required Value before $3^{rd}$ clock
0 0 X 0 X X X X Required Value before $2^{nd}$ clock
X X X X X X X X Required Value before $1^{st}$ clock

In the $2^{nd}$ row (from top). Following values are also possible.

0 1 1 1 1 0 X X Required Value before $3^{rd}$ clock
1 1 1 1 1 0 X X Required Value before $3^{rd}$ clock

So non of the options are matching. I hope this helps.

ping @Krish__, @rahul sharma 5,  @Red_devil, @Shivam Chauhan, @Tuhin Dutta, @Anu007,  @Ashwin Kulkarni @reena_kandari  and @srestha ji

1 comment

Whats the final conclusion on this, as 3rd cycle for all 4 options is 111 are none of the answers correct, if so was grace marks given in Gate 2005 for this questions
0
0
Answer:

Related questions