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A $4$-stage pipeline has the stage delay as $150,120,160$ and $140$ ns respectively. Registers that are used between the stages have delay of $5 \mathrm{~ns}$. Assuming constant locking rate, the total time required to process $1000$ data items on this pipeline is

  1. $160.5 \mathrm{~ms}$
  2. $165.5 \mathrm{~ms}$
  3. $120.5 \mathrm{~ms}$
  4. $590.5 \mathrm{~ms}$
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total cycle= k+n-1

k is number of stage and n is total instruction

then total cycle=4+1000-1=1003

and each cycle take  =max(150,120,160,140) +delay of register (5)=165 nsec

hence total time =165*1003=165495 nsec=165.5 micro sec
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  • Pipeline time to process 1000 data items

  • ⇒ Time taken for 1st data item + Time taken for remaining 999 data items

  • ⇒ 1 x 4 clock cycles + 999 x 1 clock cycle

  • ⇒ 4 x cycle time + 999 x cycle time

  • ⇒ 4 x 165 ns + 999 x 165 ns

  • ⇒ 660 ns + 164835 ns

  • ⇒ 165.5 ms

  • The Correct Answer is 165.5 ms

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