Made Esy Test Series 2022 | COA | Subject wise Q.no 17

Question

 

 

** MSQ **

Consider the following sequence of micro-operations (μO) on a system used for instruction fetch:

Where MAR is memory address register, PC is program counter, MBR is memory buffer register and IR is instruction register. And Mem[MAR] means reading data from memory location provided in MAR. Assume each μO takes 1 cycle. Which of the following μO’s can execute parallely without conflict.

1. μO2 and μO3
2. μO1 and μO3
3. μO4 and μO3
4. μO2 and μO4

 

Comments

option A and C

Answer 1

Provided key is (a,b,c)

Reason says: They have no common operand
BUT in opt b and c, both uses local bus for transfer, as PC is incremented and also stored via the local bus, so how can they be executed in one cycle ?? Anyone plz
Is there any dedicated hardware to increment PC, or we bring PC to ALU via local bus, increment it, and send it back to PC register via local bus

Comments

If we consider split cycle scenario we can divide the cycle into two halves such that in the first half PC is written into MAR and in the second half PC is incremented and moreover in the question it is saying “can execute parallely without conflict”. So that is why I guess b is also a viable option as this scenario is possible. That is why a,b,c are possible options. 

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@Sunnidhya Roy i agree to your argument, but we should not assume split phase if not mentioned

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@Shubhodeep In the question it is mentioned “can execute paralley” that is why I am saying b can be a viable option.