BARC 2015

Question

Operand is fetched from memory During

(A) fetch phase

(B) execute phase

(C) decode phase

(D) read phase

Answer 1

The correct answer is (B) execute phase.

In a typical computer architecture, the fetch-execute cycle is the basic operation performed by the central processing unit (CPU). The cycle consists of two main steps: the fetch phase and the execute phase. During the fetch phase, the CPU retrieves the next instruction from memory. The instruction is then decoded during the decode phase to determine what operation needs to be performed. The operands required for the operation are then fetched during the execute phase. Once the operands are fetched, the CPU performs the operation and stores the result in the appropriate memory location during the write-back phase. Therefore, the operand is fetched from memory during the execute phase of the fetch-execute cycle.

Comments

Is this the same for RISC processors? There are 5 stages in RISC which are IF, ID, OF, EX, and WB. So in this case the operand fetch takes place in the third stage.

You explained a generalized processor containing 4 stages, where the operand is stored if it fetches them at the IF stage.

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You are correct that the instruction execution cycle and the specific stages involved can vary depending on the processor architecture. The example I provided was a generalized explanation of a classic RISC architecture.

In a typical RISC processor, the five stages are Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Write Back (WB).

During the IF stage, the processor fetches the instruction from memory. The instruction is then decoded in the ID stage, and the operands are retrieved from registers or memory during the EX stage. The operation is then executed, and the result is stored back in memory during the MEM stage. Finally, the result is written back to the appropriate register during the WB stage.

So, in RISC processors, the operand fetch typically takes place during the EX stage, which comes after the ID stage.

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isnt your answer contradicting itself?

The operand is fetched from memory during the fetch phase.
 

The operand is then fetched from memory during the read phase, 

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You are correct, and I apologize for the confusion. My previous answer was incorrect and contradictory. I apologize for any confusion this may have caused.

To clarify, in a typical RISC processor, the five stages are Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Write Back (WB). During the IF stage, the processor fetches the instruction from memory. The instruction is then decoded in the ID stage, and the operation to be performed is determined. During the ID stage, the processor also identifies the operands involved in the operation.

Then, during the EX stage, the processor fetches the operands from registers or memory and performs the operation. Finally, during the MEM stage, the result of the operation is stored back in memory. In the last stage, the WB stage, the result is written back to the appropriate register.

Therefore, in a typical RISC processor, the operand fetch typically takes place during the EX stage, after the ID stage. I apologize for any confusion my previous answer may have caused, and I hope this clears things up.