GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 50

Answer 1

Comments

@Sachin Mittal 1 Satisfied with option D as index+tag bits are matching, how option A and B are correct as in both options tag+index bits are not matching?

---

ques says which can be in the cache SIMULTANEOUSLY, so if they belong to the same index then they cannot be in the cache simultaneously in direct mapped, thats why A ,B correct, they will map to different cache index so no prb.

---

@DevDh what if it were like 2-way-set-associative cache? In this case what will be answer?

---

in that case we will have 2 ^ 12 blocks in the cache (from direct mapped index we get this) then, since it is 2 way, we will calculate the no. of “sets” = 2^12 / 2^1 = 2^11 now we have 11 bits that tell us set no. ignoring the offset (LSB 4 bits) now , just convert the options into the binary to check if any of the addresses match, BUT ! since each set is 2 way even if they match they can exist simultaneously in the cache, so yeah? hope this calculations correct

---

In options A and B, we have different tag and index values and hence they will be mapped to different cache lines ---> they can be present in the cache simultaneously.

For option D, tag and index bits are exactly the same, only offset bits are different and hence these addresses are of the same block!

---

What does it mean by

Having Same Tag part and Different Tag part for two addresses if nothing else is given.

What does this Tag part represent? @GO Classes 

---

Actually the question is asking for simultaneous transfer of the given address from main memory to cache.So simultaneous transfer is possible only for 2 cases-

1-Given address are present in same block(means same tag and same cache index)->matches option D

2-Given address are present in 2 different blocks who are never going to be placed in same cache index(means different index no)->matches option A and B.