GATE CSE 2005 | Question: 80

Question

Consider the following data path of a $\text{CPU}.$

The $\text{ALU},$ the bus and all the registers in the data path are of identical size. All operations including incrementation of the $\text{PC}$ and the $\text{GPRs}$ are to be carried out in the $\text{ALU}.$ Two clock cycles are needed for memory read operation – the first one for loading address in the $\text{MAR}$ and the next one for loading data from the memory bus into the $\text{MDR}.$

The instruction "call Rn, sub” is a two word instruction. Assuming that $\text{PC}$ is incremented during the fetch cycle of the first word of the instruction, its register transfer interpretation is

$\text{Rn} \leftarrow \text{PC} + 1$;

$\text{PC} \leftarrow \text{M[PC]}$;

The minimum number of CPU clock cycles needed during the execution cycle of this instruction is:

• A. $2$
• B. $3$
• C. $4$
• D. $5$

Comments

@srestha

Does they asked for it?

Even if they didn't ask then how are you planning to do it ?

They asked to show the execute cycle of "call Rn, sub”.

And that maynot even require PC,GPR,S or T(as shown in diagram) , those thing when this subroutine is calling.

Please, can you write down the steps for $"call\ Rn,sub"$ which you think is valid.

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@Kushagra गुप्ता

I think like this.

Though the question is asking for execution cycle, but in this subroutine call instruction, there is nothing to execute. Like add, subtract or branching like operation. 

So, what is need to be perform here, nothing but Fetch cycle.

Steps are

1) First Fetch address of the subroutine. Put MAR value in PC.

2)Increment PC value. As it is a memory read operation, wait for Memory Function Complete Signal(WMFC).

3) Fetch data By MDR and put it in IR.

Let me know, if it is correct.

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someone please provide video lecture link related to this concept

Answer 1

• $\text{MAR} \leftarrow  \text{PC}\qquad \to1$ cycle
• $S \leftarrow \text{PC}$ (Since these two actions are independent they can be done in same cycle)
• $\text{MDR} \leftarrow \text{M[MAR]}\qquad \to 2^{nd}$ cycle (System BUS)
• $\text{Rn} \leftarrow S +1$ $(\text{ALU}$ Is free and the two actions are independent.) (Internal BUS)
• $\text{PC} \leftarrow \text{MDR}\qquad \to 3$rd cycle

Therefore $3$ cycles needed.

A rough sketch:

Correct Answer: B

Comments

In the second cycle S + 1 will be calculated but the result of increment can't be stored in the RN in the same cycle along with MDR <- M[MAR] as this will bring two different data on the bus in the same clock cycle.

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can someone elaborate?? i am unable to understand this concept.

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Even I think so. So it should be 4 cycles. I m unable to understand 3 cycles as answer

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@sushmita, Why 4 cycles ?

Tell me what will happen if i enable $\text{PC}_{out} \text{, MAR}_{in} \text{, and S}_{in}$ ?

Enabling  $\text{PC}_{out}$ means content of  $\text{PC}$ is available on Dta Bus, now at the same time if i enable $\text{ MAR}_{in} \text{, and S}_{in}$ that means content of $PC$ will be loaded into  $\text{MAR}$ and  $\text{S}$.

Yes we can load PC value (or any register value) to many registers in ONE cycle.

$T_0$ : $ MAR \leftarrow PC \\ S \leftarrow PC$

$T_1$ : $ MDR \leftarrow M[MAR] \text{  Operation on system bus (address bus)}

\\ R_N  \leftarrow S+1  \text{  Operation on internal bus }$

$T_2$ : $PC \leftarrow MDR$

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Thanx sachin. That was my doubt. i was confused about the 2 buses.

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how to  know whether the question assumes different buses?

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Welcome :)
Question does not assume anything, it is ALWAYS the case that system bus and internal buse needed everywhere.
System Bus: To let interact the CPU with external components. eg- Memory, I/O.
Internal Bus: To let interact the CPU with internal components. eg- Register file, ALU.
 

 

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When do we load 1 in to temporary register to add it with PC?will it not take any extra cycle ,loading an immediate data?Or we are assuming it is already loaded ?

It is mentioned that  increment operation ALU is used ,but still we need to load 1 into T,when are we loading that 1 into T ?As T is connected to bus so it must come via bus.

Please someone clear this doubt

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@rahul

what I am getting there are not separate clock cycles for each instruction

Fetch is taking 2 clock cycles and execute takes 1 clock cycle

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@srestha ,my doubt is how 1 is loaded into the second operand of ALU while incrementing PC

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what is the best source to read about control unit design and CPU organization..?

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How can you conclusively say that ALU operation and writing to the register file happens in same cycle.This, surely depends upon the architecture.

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@Arjun sir,

Inhttps://gateoverflow.in/1402/gate2005-79,we have taken 2 cycles to load S and T.But in given question here,to Perform S+1 we need to load 1 into T. In which cycle we are doing this?Can someone explain this?

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yeah 3 cycle is final answer

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tucey great ho sachin paaji

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great explanation riya

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Is it a single bus organization or two bus organization?

I think it is a two bus organization

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Shouldn't MAR ← PC, and MDR ← M[MAR] be a part of the fetch cycle instead of the execution cycle as it was in the first part of the question?

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@Ajit J yes that the part of IF that MAR <- PC and MDR <- M[MAR] but after instruction fetch it comes to execute so what we wanted to execute we wanted to give PC value to Rn and  so we have to first access the MAR and go to Rn  so and get the value through DATA BUS to MDR that's why .......

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I think, INC  operation will be performed. So there is no need to load 1.

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nice microprocessor

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$T_0$ : $ MAR \leftarrow PC \\ S \leftarrow PC$

why two steps are required here? can we not do it in one step?

@Shaik+Masthan can u help me plz. 

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@srestha

They can be and are already done in one step only.

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How r u telling, it could be done in one step?

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srestha Ma'am see Sachin sir's comment https://gateoverflow.in/43568/gate2005-80?show=111365#c111365

 

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Why we need two steps: MDR<- M[MAR]  and PC<-MDR , when we can directly do as: PC<- M[MAR]  because both PC and memory are connected together via the data bus. why is it necessary to first transfer data from memory to MDR then from MDR to PC. I think we only need MDR when we require ALU, isnt it?

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It is given in the question that All operations including incrementation of the PC and the GPRs are to be carried out in the ALU.

It means to do S +1  through  ALU we need to store 1 in T first and then do Rn <---- S + T. It will take one additonal CPU cycle (for T <---- 1)

someone plese clarify this

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 Sachin Mittal 1Sir, I got your explaination but using your explaination I couldnt Solve this Question https://gateoverflow.in/731/gate2001-2-13 .  According to me answer should be 2 Of this question. 

Explaination;

T0: MAR← SP   (SINCE THERE IS A CONNECTION BETWEEN MUX OF SP AND DEMUX OF MAR I ASSUME THIS TRANSFER DOES NOT USE INTERNAL BUS.

T0: MDR← R ( THIS USES iNTERNAL BUS)

T1: SP<-SP-1 (LOCAL)   

T1: M[MAR]<-MDR

 

Can somebody clarify?

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The instruction "call Rn, sub” is a two word instruction. Assuming that PC is incremented during the fetch cycle of the first word of the instruction

What’s the purpose of the above statements in question?

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dude in question it is given that pc is incremented in fetch cycle itself and we are asked to find out no of cycles in execution cycle. So do not bother about pc increment, just 1 cycle for PC to MAR

                                                                                              2 cycle for MAR to memory to MDR

                                                                                              3 cycle for MDR to PC

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@Sachin Mittal 1 Sir, thank you for the wonderful comment. I have one doubt, as why do we need one more cycle for $PC \leftarrow MDR$ ? Can’t we do it in the 2^nd cyce itself? Because it is just a $reg-reg$ transfer? Or is it because even the Internal Bus is busy? But can’t more than one operation be done in the internal bus simultaneously in one clock cycle?

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during the 2^nd cycle , we are using the bus to transfer the result of (PC+1) into Rn.
That’s why we can’t use it to transfer PC← MDR  @Abhrajyoti00

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No, @Alekhyo Banerjee. That's not the reason. I got it now. 

We could have done $PC <- MDR$ in the same 2nd cycle only, because reg-reg transfer opn takes 1 cycle and we can do many reg-reg transfer opn in 1 cycle. The problem is that in the 2nd cycle there is a operation of $MDR <- M[MAR]$. Till the value comes into $MDR$, how can we store the value of $MDR$ in $PC$? That's the reason why we need to wait more cycle.

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But the question says that the Instruction is of 2 words, so 1st word is fetched during Fetch cycle, and the 2nd word of the instruction is fetched in the Execution cycle (Instruction Decode cycle) isn't it? Then 1 more cycle should be added to 3 cycles (4 cycles in total). Correct me if I am wrong.

Answer 2

_{Rn <= Pc+1}

_{Pc<= M[Pc]}

The sequence of instruction take place 

 

I Cycle : PC _out  , S_{in ,} MAR_in (MAR can be loaded with PCout

II Cycle: S _out  , ALUincrement  , R_{n in}

III Cycle: MDR_{out  ,}   PC_in  (MDRout can be performed once MARin has been performed)   therefore 3 cycle required

 

Comments

why we need to store PC value in MAR and Sin??and can we transfer PC content to Sin and MAR in same clock cycle?

Thanks

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Obviously we can store in same clock because once the content of PC is on bus both the registers MAR and S can activate their load input to take the data on the bus.

Answer 3

Hi Guys,

Although many people have provided correct answer but It seems people want to see complete picture so just adding this answer.

So Answer is B part.

In above explanation $S$ is a temporary ALU register. Notice data to and from memory comes and goes via MDR that too via separate BUS.

If provided information is not correct then please notify.

Comments

@Chhotu ji

can u share the source, from where u given ans?

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can u share the source, from where u given ans?

@srestha ji,

This answer is not available anywhere. I derived it based on whatever is mentioned in question and standard text book.

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very nice explanation...but i have one doubt

the pc will increment to 2 in instruction fetch phase  or it will increment to 2 after instruction decode phase?

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Great solution considering the book Hamacher et al.

A correction by the way, the register Rn_in takes input from MAR_in

Answer 4

1)PCout ,MARin,Rin

2)MDRout ,PCin

2 cycles to read

so total 3  cycles

Comments

can you explain your answer somewhat..as i am not able to understand any of the answers.

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@Arjun Sir.

I am getting this. Question says, ”PC is incremented during the fetch cycle of the first word of the instruction”. So increment not needed during execution phase.

Please tell if this is correct or not.

T1: $PC_{OUT}, MAR_{IN}, Rn_{IN}, READ$

T2: $WMFC (i.e. MBR\leftarrow MEMORY)$

T3: $MBR_{OUT}, PC_{IN}$