Hamacher-DMA

Question

The average seek time and rotational delay in a disk system are 6ms and 3ms, respectively.  The rate of data transfer to or from the disk is 30 Mbytes/sec and all disk accesses are for 8 Kbytes of data. Disk DMA controller, the processor and the main memory are all attached to a single bus. The bus data width is 32 bits and a bus transfer to or from the main memory takes 10 nano seconds.
a) what is the maximum number of disk units that can be simultaneously transferring data to or from the main memory?
b) what percentage of main memory cycles are stolen by a disk unit, on average over a long period of time during which a sequence of independent 8K-byte transfers takes place?

Comments

But 1st one asks about disk units,i.e simultaneous disk accesses done .

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@-Kapil I think its not asking about how much disk units are simultaneously being accessed because it will depend upon the hardware architecture( e.g. no of heads etc.) but what amount of data can be transferrred to memory in one go.

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@Arjun

sir why here we have considered rotational latency and seek latency and not in this https://gateoverflow.in/3694/gate2004-it-51 ?

please check it

Answer 1

Average seek time = 6ms

Average rotational delay = 3ms

Data transfer rate = 30MB/sec

All disk accesses are 8KB of data. Here, they are assuming that whenever disk is accessed, it either reads or writes 8KB of data.

Data bus width is given to be 32 bits and a bus transfer to / from MM takes 10 ns.

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A). Memory Bandwidth is the rate at which data can be read or stored into the memory. Also, known as MM transfer rate.

Transfer rate according to the question for a disk = 30MB/sec.

It is also given that 32 bits can be carried by the bus to the main memory in 10 ns, hence, what is the MM transfer rate then ?

MM tramsfer rate => 32 bits / 10 ns = 400 MB/sec

• Now, a disk can transfer 30 MB in a sec whereas, MM can attain upto 400 MB/sec, hence, maximum disks that can transfer simultaneously = 400 / 30 = 13.333.
• If I take it as 14 (approx) , then total rate will be 420 MB/sec, which is out of scope for MM .
• So, at the best, 13 disks are capable of transferring simultaneously .

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B). Question asks about using burst mode approach to be used to transfer 8KB of data.

So, for accessing 8KB of data, how much time is needed :

=> Time to find the specific track (seek time) + Time to reach the specific sector on the track + Time to transfer 8KB of data (Here, Average seek time and Average rotational delay are given, so will assume directly these times)

=> 6 + 3 + (8KB / 30MB/sec)

=> 9.26666

=> 9.27 ms

This says, that in a time period of 9.27 ms, 8KB of data can be accessed on the disk.

But, we need to access the given data using cycle stealing. DMA controllers operate in a cycle stealing mode here particularly in which they take over the bus for each byte (word) of data to be transferred and then return the control to the CPU.

How this mechanism works ?

• CPU provides the start address and the word count to DMA controller, and the word count specifies the data to be transferred in one cycle stolen .
• And each time the disk is ready to transfer a byte, it asserts its DMA request line to the DMA controller .
• The DMA controller then, asserts the CPU through HOLD request.
• When the CPU suspends the execution of the current program, it asserts the hold acknowledge HLDA signal to the DMA controller.
• DMA controller then puts the MM address on the address bus, asserts either MEMR + IOW or MEMW + IOR on the control bus . (MEMR = Memory read, MEMW = Memory write and same for I/O )
• Disk then responds to the DMA ack. signal by reading or writing, its data to the data bus.
• And, atlast the same time, the MM responds to the control signal which causes the data to be read/written directly from/to memory.

Hence, we found that 8KB of data can be transferred in 9.27 ms.

Now, the data transfer is done by the DMA controller, which will operate at memory cycle time, so in 10 ns, 32 bits can be send.

=> 10 ns = 32 bits 

=> 1 sec = 32 * 10⁸ bits can be send.

But, data on the disk can be accessed in 

=> 9.27 ms = 8KB

=> 1 sec = 6.9039 * 10⁶ bits

Hence, percentage of memory cycles stolen by a single disk unit :

=> 6.9039 * 10⁶ / 32 * 10⁸ 

=> 0.002157 * 100

=> 0.2157 = approx 0.216 % 

Comments

@kapil,one question please..in second part,for cycle stealing ,transfer is done for 1 byte/word at a time then the bus is given back to cpu.so the cpu is actually idle for the time required to transfer 1 byte by the data bus.

is the question asking about the cycles stolen from cpu..i.e the time during which cpu is idle?or is it asking about memory cycles stolen by disk unit..?

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how is cycle stealing mode  utilised here in second part..not understanding it..as you have not considered the time to transfer 1 byte..??:-(

what difference if it would have been the burst mode..8KB in numerator then?

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What is the difference between "memory cycles stolen by disk unit" and "cycles stolen from cpu" ?

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memory cycles stolen by disk unit means the time disk is taking for transferring its data

and cpu cycles stolen is the time cpu is idle when DMA takes control.

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So, both are same, rt ?

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oh yes..sorry for that,,:-/

but tell,how have u used cycle steal concept here?as 1 byte time should be considered na?

pls excuse me for all the silly doubts..

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which a sequence of independent 8K-byte transfers takes place

Means in 1 cycle, 8KB are read or written in cycle stealing .

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so, you mean instead of 1 byte 8Kb data is transffered in one cycle now..

so cycles stolen should'nt be 9.27/9.27 + 10

because cpu will be idle for 9.27 ms

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@Kapil,

When the disk is preparing data(Seek time,latency time)then CPUR will be free but thwne it is ready to transfer then CPU cycles are stolen.Please explain why we have stolen cpu cycles when Secondary memory is preparing data.??

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@Kapil.

We know that data is trnasfrred to the disk buffer at 30 MB/Sec.

Now, the disk controller will interrupt the CPU after every 1 Byte is ready for transfer.

i.e. disk controller will interupt the CPU after every 1/(30 M) sec = (1/30) microsec

.......................(1)

 

Now, for 4 bytes are transferred to memory in 10ns

Thus, 1 byte in 2.5ns........................(2)

 

Now, in (1/30) microsec, I am using 2.5ns for actual transfer.

 

Thus % M.M cycles stolen = $\frac{2.5*10^{-9}}{\frac{1}{30}*10^{-6}}*100$

= 7.5%

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@Kapil. DId you verify the answer from solution manual?

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"disk controller will interupt the CPU after every 1/(30 M) sec = (1/30) microsec"

are u assuming that cycle time for 1 byte is 1sec??

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@sushant ,

 1 byte in 2.5ns" for 2.5ns,CPU wil be idle..right??and 1/30M sec is the preparation time..right??

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@Akriti.

Had it been continuous and once pipelining comes into picture, the rate will be dictated by transfer rate(given that seek and rotational latency for 1 byte is less than transfer time for 1 byte)

Here, in this example, seek and rotaional delay are larger than transfer time for 8KB and hence, they dominatd the time.

So, here it isnt continous as they have said

Independent 8K transfers

So, thats why they have added the rotational and seek latency

So, answer is correct and I verified from the manual.

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@sushant,my doubt is in cycle stealing mode,1 word or 1 byte is tranmistted per cycle,but here we are having 8KB transfer in one go..so we will consider that in 1 cycle,we are transferring 8KB

so should'nt the memory cycle stolen be

transfer time for 8KB data/tranfer time  of 8KB+ preparation time of 8Kb data

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@Akriti. No, we dont transfer 8KB in 1 cycle.

Other thing is your formula will not work because of pipelining once the transfer is continuous. Thats why we are distinguishing independent and continous data transfer here.

You will get better idea from here for interuupt driven i/o

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@sushant,ok,i got that only 1 byte is transffered per cycle..now

talking generally,what is percent of memory cycles tolen?

transfer time /transfer time + preparation time..right?i.e the time used in transffering 1 byte..right?

so can you solve the above problem by this?

i mean,why kapil has solved like

no of bits sent in 1 sec by the device/no. of bits sent in 1 sec by the DMA?

did'nt get this logic

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I will tell the logic in both conditions:

Lets consider that the infinite amount of data is being transferred and you are asked 

" what time will it take to transfer 8KB of data with starting point in between somewhere?"

I am taking this example first because you will understand the difference then.

So, when its the case like above, the rotational + seek latency start overlaping with device transfer time( i.e. the rate at which the device controller buffer is filled up). In such cases, we consider only the transfer time because unless the buffer fills up, we cant transfer the data. We dont consider the rotational + seek latency.

So, time taken to transfer 1 byte = 1 / (transfer rate)    .............(1)

But as we know that device will inteerupt the CPU when after every 1 byte is ready in its buffer.

So, if the transfer rate 2 byte/sec, then  device will interrupt the CPU every 0.5 sec indicating that 1 byte is coming into its buffer every 0.5 sec and needs to be transferred to memory before the next byte comes in(else the controller buffer will overflow).

So, in between  the 2 interrupts( 0.5 sec), 1 byte must be transferred to M.M. During this transfer, the bus wont be available to CPU.

Now, for transferring to M.M, time taken = 1 byte / (M.M trnsfer rate)   ...........(2)

Thus, % cycles stolen = (2) / (1)

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Now, consider this example. They say 

Independent 8K transfers

which means that they havent asked us to chosse any starting point during infinite data transfer.

Now, there are 2 cases:

1. (seek + rotational ) latency  <  transfer time

     Here, I simply overlap the (seek + rotatinal) latency with transfer time due to concept of pipelining if the data transfer is huge

2. (seek + rotational ) latency  >  transfer time

    I cant overlap because (seek + rotational ) latency dominates over transfer time(  here 9 ms over 0.26ms)

So, now,  instead of just considering the transfer time, they have added the (seek + rotational ) latency to tranfer time.

So, % cycles stolen = (time to transfer 8KB data over bus) / (time to prepare and transfer 8KB data) 

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i guess,i have understood your point your point sushant..here we are not fetching continously,hence we need to take rotaion and seek time..that is ok.i understood your first case as well as second case.

but the answer given above is like

number of bits transffered in 1 sec by disk/bits sent in 1 sec by DMA ............/ /did'nt get this logic that why are we considering number of bits in 1 sec..?

should'nt this be

time to transfer 1 byte by DMA/preparation time for 1 byte by disk + transfer time for DMA

because only during transfer time of DMA only,CPU is idle,,so that should be at the numerator

please correct me

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see this
8K/30M = 0.27 ms is needed to transfer 8K bytes to/from the disk. Seek and
rotational delays are 6 ms and 3 ms, respectively. Therefore, 8K/4 = 2K words
are transferred in 9.27 ms means it need 2K cycles. But in 9.27 ms there are
(9.27 * 10^-3)/(0.01*10^-6) = 9.27 *10³ memory (word) cycles available. Therefore, over a long
period of time, any one disk steals only (2/927)* 100 = 0.2% of available
memory cycles

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@Akriti. Yes, you are true.

Calculated that way, it comes out 0.22% which is almost same.

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i guess,that makes more sense to me now...

but here" But in 9.27 ms there are (9.27 * 10³)=(0.01 
10⁶) = 927 *10³ memory (word) cycles available" what is 10³ ??it is not the MM rate

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@sushant,did you solve like this?

 1 byte by DMA/preparation time for 1 byte by disk + transfer time for DMA

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solved like,

as we are tranferring 32 bits in 1 cycle time ,so 4 bytes which need 10 ns by DMA

and 8KB is tranferred by disk in 9.27 sec,so 4 bytes in 4635 ns

hence,%memory cycles are 10ns/(10ns+ 4635) *100

thi coming to be 0.21

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@Akriti. Sorry. I miscalculated it. Your approach isnt giving correct answer.

Thats because we wont be counting seek and rotational latency again and again.

 

If we count per byte cycles stealed, we miss on initial seek and rotational latency which is dominant.

 

This is very complicated indeed :P  My head not working

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@sushant see now it is corrected

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ok sushant..:-P,but i did nt understand kapil's method tough.anyways,thanks...

..my mind also not working,and i sriously i dun understand such types of questions.

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@Akriti. For the latest exlanation you gave, you averaged the total time for 4B.

Thats why its giving correct :)

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@sushant,,yes i guess so

and @saurabh.pls explain this

" But in 9.27 ms there are 
(9.27 * 10^-3)/(0.01*10^-6) = 9.27 *10³ memory (word) cycles available"

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see 1 cycle time=10 ns=0.01*10^-6s
hence  in 9.27 ms there are  
(9.27 * 10^-3)/(0.01*10^-6) = 9.27 *10³ memory (word) cycles available

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ooh,u mean in 10ns,we can transfer 1 word,so in 9.27 msec,we can transfer 9.27ms/10 ns words..

alright..thanks for clarifying

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yes exactly same

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this is really confusing at first but after a lot of thought I think I have figured out the easiest way to do this is

x= data prep time= time to read  4B

y = 10ns

%cycle stealing = y/(x+y)

am I right?

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Are u sure we will add seek time in total data preparation time?

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They have said independent 8K transfers - meaning first go to the appropriate position and then start fetching data. So, seek time is added

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@sushant in dma do we always have to use x/(x+y) or x/y is used  I have seen questions and solutions with both formulas can you explain what to use when

I know interrupt I/o uses x/y but not sure about dma

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For the part B:)

As we need to transfer 8kb and Word Siz=4b so after every 4b of data disk with interrupt processor and takes 10 ns.After the first interrupt where seek and latency time has been utilized ,after that it will be just the time to transfer 4b(excluding seek and latency time) and after that time it will take 10ns of time.

So can we say time to 10ns/transfer4b will be answer?

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@pankaj joshi

I hope this link and the links in that problem solution help you:

https://gateoverflow.in/116524/coa-dma-doubt?show=130586#c130586

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@Sushant

Here we are transferring 8k bytes in cycle stealing mode or in burst mode?

As per the solution it is cycle stealing mode ,but why cant we use the burst mode here?Independent 8k byte transfer means seek and latency time will be considered.But why cycle stealing mode is used

And in question:-https://gateoverflow.in/1393/gate2005-70

How do we know that whether we need to add disk data preparation time in denominator or not?I means whether to use pipelining concept in cycle stealing or not?

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..................

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Got it. Thanks kapil.

So when disk has sent 1 byte then again we will move head to desired track and sector or will it be a continuous transfer?

From the answer we are saying how much data disk can transfer in 1 sec and that includes seek and rotaional time ,so does that means we always need to position disk with seek and latency time for every byte in cycle stealing mode?

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.......................... .

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@Kapil:-

1.If the question wording is:-   what percentage of main memory cycles are stolen by a disk unit, on average over a long period of time during which   8K-byte transfers takes place?

Then which mode will it be?

2.1.If the question wording is:-   what percentage of main memory cycles are stolen by a disk unit, on average over a long period of time during which  Disk transfers 8Kb actively"

In 2nd point will it be burst mode,because disk is transferring actively?

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@Rahul

I missed one thing here. Sorry for that .

This is not cycle stealing mode. It is a burst mode. Actually, we will transfer the data 8KB only when it is collected as a buffer and main concentration lies with the fact that how to transfer that data, either by burst mode or cycle stealing. Here, it is not saying explicitly cycle steal, so it is a burst mode.

I edited my answer and previous comments.

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@Kapil .

1. But still in your answer ,Question asks about using burst mode approach to be used to transfer 8KB of data."

and then it says that "But, we need to access the given data using cycle stealing. "

I didn't understand that part.

2.Also, second part asks how many memory cycles stolen,but in burst mode cycles will not be stolen?Am i missing something here?

3.And if it is a burst mode,then DMA will hold the bus for the complete duration of transfer,then why are we saying it is .02% stolen?

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What does bus transfer mean?

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https://itconnect2011.files.wordpress.com/2012/03/computer-organization-hamacher-instructor-manual-solution-chapter-51.pdf

Check the solution of the problem 5.27.Above is the link of the solution manual of the book.

Answer 2

for part b)

It is like when the buffer accumulated 8KB data it will ask the CPU for the buses. So in one cycle CPU will be held up for the bus cycle time needed to transfer 8KB data.

Disk transfer time for 8KB data= 800/3 microsec+ seek time+ Rotational latency=6000+3000 microsec+ 800/3 microsec=9286666.66 microsec

cycle time= 8000/4 * 10=2000 microsec

% of cpu cycles stolen= 2000/9286666.66=0.22%